DATASHEET HA-5137A. Features. Applications. Ordering Information. Pinout. 63MHz, Ultra-Low Noise Precision Operational Amplifier

Transcription

1 DATASHEET HA-5137A 3MHz, Ultra-Low Noise Precision Operational Amplifier The HA-5137 operational amplifier features an unparalleled combination of precision DC and wideband high speed characteristics. Utilizing the Intersil Dielectric Isolation technology and advanced processing techniques, this unique design unites low noise 3nV Hz precision instrumentation performance with high speed (2V/ s) wideband capability. This amplifier s impressive list of features include low V OS (1 V), wide gain bandwidth (3MHz), high open loop gain (1V/mV), and high CMRR (12dB). Additionally, this flexible device operates over a wide supply range ( 5V to 2V) while consuming only 1mW of power. Using the HA-5137 allows designers to minimize errors while maximizing speed and bandwidth in applications requiring gains greater than five. This device is ideally suited for low level transducer signal amplifier circuits. Other applications which can utilize the HA-5137 s qualities include instrumentation amplifiers, pulse or RF amplifiers, audio preamplifiers, and signal conditioning circuits. This device can easily be used as a design enhancement by directly replacing the 725, OP25, OP, OP7, OP27 and OP37 where gains are greater than five. For the military grade product, refer to the HA-5137/3 data sheet. Features FN29 Rev 5. Slew Rate V/ s Wide Gain Bandwidth (A V 5) MHz Low Noise at 1kHz Low V OS V High CMRR dB High Gain V/mV Applications High Speed Signal Conditioners Wide Bandwidth Instrumentation Amplifiers Low Level Transducer Amplifiers Fast, Low Level Voltage Comparators Highest Quality Audio Preamplifiers Pulse/RF Amplifiers For Further Design Ideas See Application Note AN553 Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE 3nV/ Hz PKG. NO. Pinout HA-5137A (CERDIP) TOP VIEW HA7-5137A-5 to 75 Ld CERDIP F.3A BAL 1 BAL -IN IN V V- 5 NC FN29 Rev 5. Page 1 of 9

2 Absolute Maximum Ratings T A =25 o C Voltage Between V and V- Terminals V Differential Input Voltage (Note 1) V Output Current Full Short Circuit Protection Operating Conditions Temperature Range HA-5137A o C to 75 o C Thermal Information Thermal Resistance (Typical, Note 2) JA ( o C/W) JC ( o C/W) CERDIP Package Maximum Junction Temperature (Hermetic Package) o C Maximum Storage Temperature Range o C to 15 o C Maximum Lead Temperature (Soldering 1s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. For differential input voltages greater than.7v, the input current must be limited to 25mA to protect the back-to-back input diodes. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = 15V, C L 5pF, R S 1 PARAMETER TEST CONDITIONS TEMP. ( o C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage V Full - 3 V Average Offset Voltage Drift Full -.2. V/ o C Bias Current 25-1 na Full - 2 na Offset Current na Full na Common Mode Range Full V Differential Input Resistance (Note 3) M Input Noise Voltage (Note ).1Hz to 1Hz V P-P Input Noise Voltage Density f = 1Hz nv/ Hz (Note 5) f = 1Hz nv/ Hz f = 1Hz nv/ Hz Input Noise Current Density f = 1Hz pa/ Hz (Note 5) f = 1Hz pa/ Hz f = 1Hz pa/ Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain R L = 2k, V/mV V = 1V Full 12 - V/mV Common Mode Rejection Ratio V CM = 1V Full db Minimum Stable Gain V/V Gain-Bandwidth-Product f = 1kHz 25 - MHz f = 1MHz MHz PUT CHARACTERISTICS Output Voltage Swing R L = V R L = 2k Full V Full Power Bandwidth (Note ) khz Output Resistance Open Loop Output Current ma TRANSIENT RESPONSE (Note 7) Rise Time ns Slew Rate V = 3V V/ s Settling Time Note s Overshoot 25-2 % POWER SUPPLY CHARACTERISTICS Supply Current ma Full - -. ma FN29 Rev 5. Page 2 of 9

3 Electrical Specifications V SUPPLY = 15V, C L 5pF, R S 1 (Continued) TEMP. PARAMETER TEST CONDITIONS ( o C) MIN TYP MAX UNITS Power Supply Rejection Ratio V S = V to 1V Full - 2 V/V NOTES: 3. This parameter value is based upon design calculations.. Refer to Typical Performance section of the data sheet. 5. The limits for this parameter are based on lab characterization, and reflect lot-to-lot variation. Slew Rate. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = V 7. Refer to Test Circuits section of the data sheet. PEAK. Settling time is specified to.1% of final value for a 1V output step and A V = -5. Test Circuits and Waveforms IN - 1.k 5pF FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT IN IN Vertical Scale: Input = 1V/Div. Output = 5V/Div. Horizontal Scale: 1 s/div. LARGE SIGNAL RESPONSE Vertical Scale: Input = 2mV/Div. Output = 1mV/Div. Horizontal Scale: 1ns/Div. SMALL SIGNAL RESPONSE IN 1 2N1 5k 15V - -15V 2k 15V 2k 5pF TO OSCILLOSCOPE NOTES: 9. A V = Feedback and summing resistors should be.1% matched. 11. Clipping diodes are optional. HP52-21 recommended. FIGURE 2. SETTLING TIME TEST CIRCUIT FN29 Rev 5. Page 3 of 9

4 FN29 Rev 5. Page of 9 Schematic Diagram Q D V Q N5 7 QN57 V- R 1 C 7 D 1 R 2 Q Z5 Q D59 Q N2 R 15 QP37 Q P5 Q N12 R Q D R5 R SUBSTRATE Q P55 Q N25 R 25 R 1 Q P32 Q N19 R 1A Q N3 Q N2 3 2 INPUT Q N51 R 9 1 BALANCE Q N2A Q D53 Q D22 Q D23 Q P27 Q N2A C Q P3 Q P3A Q N39 Q N1 Q P35 Q N2 R Q N11 R 1 Q N R 2 Q N7 R 2A C 1 Q D9 Q N52 Q N Q P2 Q D1 Q P Q D5 Q N1A R1 Q N1 C 5 Q N13 C -INPUT Q N1 Q N R 1 Q N15 R 7 R 3 Q N9 Q P3 Q P17 Q N5 R 2 C 2 R 22 Q N7 Q N R 23 R 21 Q P Q P1 R 17 Q P3 Q P2 Q N1 R 19 C 3 Q N5 Q N29 Q P3 Q D33 Q D3 Q N2 R 12 - PUT R 13 Q P21 HA-5137A

5 Application Information R P 1K V 5 NOTE: Tested Offset Adjustment Range is V OS 1mV minimum referred to output. Typical range is mv with R P = 1k. FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT C S R 1 - R 1 R 2 R 3 - R 2 R 3 C 3 NOTE: Low resistances are preferred for low noise applications as a 1k resistor has nv/ Hz of thermal noise. Total resistances of greater than 1k on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability. FIGURE. SUGGESTED STABILITY CIRCUITS Typical Performance Curves Unless Otherwise Specified: T A = 25 o C, V SUPPLY = 15V 3 12 V S = 15V, T A = 25 o C OFFSET VOLTAGE ( V) NOISE VOLTAGE (nv/ Hz) 1 2 NOISE VOLTAGE NOISE CURRENT NOISE CURRENT (pa/ Hz) TEMPERATURE ( o C) K 1K 1K 1M FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE FIGURE. NOISE CHARACTERISTICS FN29 Rev 5. Page 5 of 9

6 Typical Performance Curves Unless Otherwise Specified: T A = 25 o C, V SUPPLY = 15V (Continued).1 T A = 25 o C 1 INPUT NOISE VOLTAGE ( V P-P ) CMRR (db) SUPPLY VOLTAGE ( V) 1 1 1K 1K 1K 1M 1M FIGURE 7. NOISE vs SUPPLY VOLTAGE FIGURE. CMRR vs FREQUENCY SUPPLY CURRENT (ma) BANDWIDTH AND SLEW RATE (NORMALIZED TO 1 AT 15V) BANDWIDTH -SLEW RATE SLEW RATE SUPPLY VOLTAGE ( V) FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY VOLTAGE ( V) FIGURE 1. BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE PSRR (db) 1 2 -PSRR PSRR GAIN (db) PHASE GAIN 9 1 PHASE (DEGREES) 1 1 1K 1K 1K 1M 1M 1 1K 1K 1K 1M 1M 1M FIGURE 11. PSRR vs FREQUENCY FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY FN29 Rev 5. Page of 9

7 Typical Performance Curves Unless Otherwise Specified: T A = 25 o C, V SUPPLY = 15V (Continued) A VOL (1kV/V) AND V (V) 17 T A = 25 o C 1 15 A VOL 1 13 V LOAD RESISTANCE (k ) FIGURE 13. A VOL AND V vs LOAD RESISTANCE SLEW RATE NORMALIZED TO 1 AT 3 o C R L = 2K, C L = 5pF, T A = 25 o C TEMPERATURE ( o C) FIGURE 1. NORMALIZED SLEW RATE vs TEMPERATURE SUPPLY CURRENT (ma) 2.2 V O = V, V S = 15V TEMPERATURE ( o C) PUT VOLTAGE (V P-P ) R L = 2K, C L = 5pF, T A = 25 o C FREQUENCY (MHz) FIGURE 15. SUPPLY CURRENT vs TEMPERATURE FIGURE 1. V MAX (UNDISTORTED SINEWAVE PUT) vs FREQUENCY GAIN (db) GAIN PHASE K 1K 1K 1M 1M 1M PHASE SHIFT (DEGREES) A CL = 25,V/V Horizontal Scale = 1s/Div. Vertical Scale =.2 V/Div., E N =. V P-P RTI FIGURE 17. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 1. PEAK-TO-PEAK NOISE VOLTAGE (.1Hz TO 1Hz) FN29 Rev 5. Page 7 of 9

8 Die Characteristics DIE DIMENSIONS: 1 mils x 5 mils x 19 mils 25 m x 15 m x 3 m METALLIZATION: Type: Al, 1% Cu Thickness: 1kÅ 2kÅ SUBSTRATE POTENTIAL (POWERED UP): V- PASSIVATION: Type: Nitride (Si 3 N ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 12kÅ 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ TRANSISTOR COUNT: 3 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout BAL HA-5137A BAL -IN IN V V- NC FN29 Rev 5. Page of 9

9 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/2, and N/21) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y1.5M Controlling dimension: INCH E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F.3A MIL-STD-135 GDIP1-T (D-, CONFIGURATION A) LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e.1 BSC 2.5 BSC - ea.3 BSC 7.2 BSC - ea/2.15 BSC 3.1 BSC - L Q S o 15 o 9 o 15 o - aaa bbb ccc M , 3 N Rev. /9 Copyright Intersil Americas LLC 2. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN29 Rev 5. Page 9 of 9