DATASHEET EL2125. Features. Applications. Ordering Information. Pinouts. Ultra-Low Noise, Low Power, Wideband Amplifier. FN7045 Rev 3.

Transcription

1 DATASHEET EL Ultra-Low Noise, Low Power, Wideband Amplifier The EL is an ultra-low noise, wideband amplifier that runs on half the supply current of competitive parts. It is intended for use in systems such as ultrasound imaging where a very small signal needs to be amplified by a large amount without adding significant noise. Its low power dissipation enables it to be packaged in the tiny SOT-3 package, which further helps systems where many input channels create both space and power dissipation problems. The EL is stable for gains of and greater and uses traditional voltage feedback. This allows the use of reactive elements in the feedback loop, a common requirement for many filter topologies. It operates from ±.V to ±V supplies and is available in the Ld SOT-3 and 8 Ld SOIC packages. The EL is fabricated using Elantec s proprietary complementary bipolar process, and is specified for operation from -4 C to +8 C. Ordering Information PART NUMBER PART MARKING TAPE & REEL ELCW-T7 F 7 (3k pcs) PACKAGE PKG. DWG. # Ld SOT-3 MDP38 ELCW-T7A F 7 Ld SOT-3 MDP38 ( pcs) ELCS CS - 8 Ld SOIC MDP7 ELCS-T7 CS 7 8 Ld SOIC MDP7 ELCS-T3 CS 3 8 Ld SOIC MDP7 Features Voltage noise of only.83nv/ Hz Current noise of only.4pa/ Hz µv offset voltage 7MHz -3dB BW for A V = Low supply current - ma SOT-3 package available ±.V to ±V operation Pb-Free Plus Anneal Available (RoHS Compliant) Applications Ultrasound input amplifiers Wideband instrumentation Communication equipment AGC and PLL active filters Wideband sensors Pinouts OUT IN+ 3 EL ( LD SOT-3) TOP VIEW VS+ VS- IN- FN74 Rev 3. May 4, 7 ELCSZ (See Note) ELCSZ-T7 (See Note) CSZ - 8 Ld SOIC (Pb-free) CSZ 7 8 Ld SOIC (Pb-free) MDP7 MDP7 EL (8 LD SOIC) TOP VIEW ELCSZ-T3 (See Note) CSZ 3 8 Ld SOIC (Pb-free) MDP7 NC 8 NC NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. IN- IN+ VS VS+ OUT NC FN74 Rev 3. Page of May 4, 7

2 Absolute Maximum Ratings (T A = + C) V S + to V S V Continuous Output Current mA Any Input V S - -.3V to V S + +.3V Thermal Information Ambient Operating Temperature C to +8 C Storage Temperature C to + C Maximum Die Junction Temperature C Power Dissipation See Curves Pb-free reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications, T A = + C, R F = 8, R G = R L = unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT DC PERFORMANCE V OS Input Offset Voltage (SO8). mv Input Offset Voltage (SOT3-) 3 mv T CVOS Offset Voltage Temperature Coefficient.8 µv/ C I B Input Bias Current -3 - µa I OS Input Bias Current Offset.4 µa T CIB Input Bias Current Temperature Coefficient.9 µa/ C C IN Input Capacitance. pf A VOL Open Loop Gain 8 87 db PSRR Power Supply Rejection Ratio (Note ) 8 97 db CMRR Common Mode Rejection Ratio at CMIR 8 db CMIR Common Mode Input Range V V OUTH Output Voltage Swing High No load, R F = k V V OUTL Output Voltage Swing Low No load, R F = k V V OUTH Output Voltage Swing High R L = V V OUTL Output Voltage Swing Low R L = V I OUT Output Short Circuit Current (Note ) 8 ma I S Supply Current. ma AC PERFORMANCE - R G =, BW -3dB Bandwidth 7 MHz BW ±.db ±.db Bandwidth 34 MHz BW ±db ±db Bandwidth MHz Peaking Peaking.4 db SR Slew Rate V OUT = V P-P, measured at % to 8% 8 V/µs OS Overshoot, 4V P-P Output Square Wave Positive. % Negative.7 % t S Settling Time to.% of ±V Pulse 4 ns FN74 Rev 3. Page of May 4, 7

3 Electrical Specifications, T A = + C, R F = 8, R G = R L = unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V N Voltage Noise Spectral Density khz.83 nv/ Hz I N Current Noise Spectral Density khz.4 pa/ Hz HD nd Harmonic Distortion (Note 3) -74 dbc HD3 3rd Harmonic Distortion -9 dbc NOTES:. Measured by moving the supplies from ±4V to ±V. Pulse test only 3. Frequency = MHz, V OUT = V P-P, into and pf load Electrical Specifications, T A = + C, R F = 8, R G =, R L = unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT DC PERFORMANCE V OS Input Offset Voltage (SO8). 3 mv Input Offset Voltage (SOT3-) 3 mv T CVOS Offset Voltage Temperature Coefficient 4.9 µv/ C I B Input Bias Current -3-4 µa I OS Input Bias Current Offset.4 µa T CIB Input Bias Current Temperature Coefficient.8 µa/ C C IN Input Capacitance. pf A VOL Open Loop Gain 8 87 db PSRR Power Supply Rejection Ratio (Note 4) 8 97 db CMRR Common Mode Rejection Ratio at CMIR 7 db CMIR Common Mode Input Range V V OUTH Output Voltage Swing High No load, R F = k V V OUTL Output Voltage Swing Low No load, R F = k V V OUTH Output Voltage Swing High R L =. V V OUTL Output Voltage Swing Low R L = V I OUT Output Short Circuit Current (Note ) ma I S Supply Current.8 ma AC PERFORMANCE - R G =, BW -3dB Bandwidth MHz BW ±.db ±.db Bandwidth 3 MHz BW ±db ±db Bandwidth 3 MHz Peaking Peaking. db SR Slew Rate V OUT = V P-P, measured at % to 8% 8 V/µs OS Overshoot, 4V P-P Output Square Wave. % t S Settling Time to.% of ±V Pulse 38 ns FN74 Rev 3. Page 3 of May 4, 7

4 Electrical Specifications, T A = + C, R F = 8, R G =, R L = unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V N Voltage Noise Spectral Density khz.9 nv/ Hz I N Current Noise Spectral Density khz. pa/ Hz HD nd Harmonic Distortion (Note ) -73 dbc HD3 3rd Harmonic Distortion -9 dbc NOTES: 4. Measured by moving the supplies from ±3.V to ±.V. Pulse test only. Frequency = MHz, V OUT = V P-P, into and pf load Typical Performance Curves A V = R L = R F = 499 R F = k R F = 8 R F = A V = R L = R F = 7 R F = k R F = 499 R F = 8 R F = - M M M M - M M M 3M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS R F FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS R F A V = - R L = R F = k R F = 3 R F = R F = 97. R F = M M M 3M FIGURE 3. INVERTING FREQUENCY RESPONSE FOR VARIOUS R F A V = - R L = R F = k R F = 3 R F = R F = 499 R F = M M M 3M FIGURE 4. INVERTING FREQUENCY RESPONSE FOR VARIOUS R F FN74 Rev 3. Page 4 of May 4, 7

5 Typical Performance Curves (Continued) R L = R G = A V = A V = A V = R L = R F = 7 A V = A V = A V = - M M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE vs GAIN - M M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS GAIN A V = - - A V = R L = A V = - R G = 3-4 M M M 3M FIGURE 7. INVERTING FREQUENCY RESPONSE vs GAIN A V = - A V = - A V = - R L = R G = -4 M M M 3M FIGURE 8. INVERTING FREQUENCY RESPONSE vs GAIN A V = R F = 8 R L = 4V PP V PP V PP mv PP 3mV PP - M M M M FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS 3.3V PP 3mV PP mv PP mv PP A V = -.V PP R F = 3 R L = V PP -4 M M M 3M FIGURE. INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS FN74 Rev 3. Page of May 4, 7

6 Typical Performance Curves (Continued) A V = R F = 8 R L = C L = 8.pF C L = pf C L = pf A V = R F = 7 R L = C L = 7pF C L = pf C L =.pf - M M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS C L - M M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS C L A V = R F = 3 R L = C L =.4pF C L =.4pF C L = 9.4pF C L =.pf C L =.pf -4 M M M 3M FIGURE 3. INVERTING FREQUENCY RESPONSE FOR VARIOUS C L A V = R F = R L = C L = 9.4pF C L =.4pF C L =.4pF C L =.pf C L =.pf -4 M M M 3M FIGURE 4. INVERTING FREQUENCY RESPONSE FOR VARIOUS C L OPEN LOOP GAIN (db) 8 GAIN PHASE 4 K K M M M - - 4M FIGURE. OPEN LOOP GAIN AND PHASE - PHASE ( ) SUPPLY CURRENT (ma) SUPPLY VOLTAGE (±V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE FN74 Rev 3. Page of May 4, 7

7 Typical Performance Curves (Continued) 3 A V =. BANDWIDTH (MHz) A V = - A V = - A V = A V = A V = - PEAKING (db).. A V = A V = - A A V = V = - A V = - A V = V S (±V) FIGURE 7. 3dB BANDWIDTH vs SUPPLY VOLTAGE V S (±V) FIGURE 8. PEAKING vs SUPPLY VOLTAGE mv/div V IN x R L = R F = 8 A V = mv/div V IN x R L = R F = 8 A V = V O V O ns/div FIGURE 9. SMALL SIGNAL STEP RESPONSE ns/div FIGURE. SMALL SIGNAL STEP RESPONSE OUTPUT VOLTAGE (.V/DIV) R L = R F = 8 A V = OUTPUT VOLTAGE (.V/DIV) R L = R F = 8 A V = TIME (ns/div) FIGURE. LARGE SIGNAL STEP RESPONSE TIME (ns/div) FIGURE. LARGE SIGNAL STEP RESPONSE FN74 Rev 3. Page 7 of May 4, 7

8 Typical Performance Curves (Continued) DISTORTION (dbc) R F = 8 A V = R L = ND HD 3RD HD DISTORTION (dbc) R F = 8 A V = R L = ND HD 3RD HD V OUT (V PP ) FIGURE 3. MHz HARMONIC DISTORTION vs OUTPUT SWING - V OUT (V PP ) FIGURE 4. MHz HARMONIC DISTORTION vs OUTPUT SWING THD (dbc) V O = V PP A V = R F = 8 R L = VOLTAGE NOISE (nv/ Hz), CURRENT NOISE (pa/ Hz) V N, V N, I N, I N, -9 K K K M M M FIGURE. TOTAL HARMONIC DISTORTION vs FREQUENCY. K K K FIGURE. VOLTAGE AND CURRENT NOISE vs FREQUENCY SETTLING TIME (ns) 4 3 V O = V PP V O = V PP V O = V PP V O = V PP GROUP DELAY (ns) 4 - A V = A V =. ACCURACY (%) FIGURE 7. SETTLING TIME vs ACCURACY - 4 FREQUENCY (MHz) FIGURE 8. GROUP DELAY FN74 Rev 3. Page 8 of May 4, 7

9 Typical Performance Curves (Continued) PSRR- CMRR (db) - -7 PSRR (db) 7 PSRR k k k M M M k k M M M M FIGURE 9. CMRR FIGURE 3. PSRR 3. R OUT ( ).. -3dB BANDWIDTH (MHz) 8 4 PEAKING BANDWIDTH 3... PEAKING (db). K K M M M TEMPERATURE ( C) FIGURE 3. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY FIGURE 3. BANDWIDTH vs TEMPERATURE 3 3 SLEW RATE (V/µs) 3 V SR - V SR + V SR - V SR + I S (ma) 9 - V OUT SWING (V PP ) FIGURE 33. SLEW RATE vs SWING FIGURE 34. SUPPLY CURRENT vs TEMPERATURE FN74 Rev 3. Page 9 of May 4, 7

10 Typical Performance Curves (Continued) - V OS (mv) - - I B + (µa) FIGURE 3. OFFSET VOLTAGE vs TEMPERATURE FIGURE 3. INPUT BIAS CURRENT vs TEMPERATURE CMRR (db) 8 PSRR (db) FIGURE 37. CMRR vs TEMPERATURE FIGURE 38. PSRR vs TEMPERATURE V O = V PP 3.8 SR (V/µs) V OUTH (V) FIGURE 39. SLEW RATE vs TEMPERATURE FIGURE 4. POSITIVE OUTPUT SWING vs TEMPERATURE FN74 Rev 3. Page of May 4, 7

11 Typical Performance Curves (Continued) V OUTH (V) 3. V OUTL (V) FIGURE 4. POSITIVE OUTPUT SWING vs TEMPERATURE FIGURE 4. NEGATIVE OUTPUT SWING vs TEMPERATURE V OUTL (V) V OUTL (V) FIGURE 43. NEGATIVE OUTPUT SWING vs TEMPERATURE FIGURE 44. LOADED NEGATIVE OUTPUT SWING vs TEMPERATURE V OUTL (V) V OUTH (V) FIGURE 4. NEGATIVE OUTPUT SWING vs TEMPERATURE FIGURE 4. LOADED POSITIVE OUTPUT SWING vs TEMPEARTURE FN74 Rev 3. Page of May 4, 7

12 Typical Performance Curves (Continued) JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. V OUTH (V) POWER DISSIPATION (W) mW 488mW SOT3- JA = C/W SO8 JA = C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 47. LOADED POSITIVE OUTPUT SWING vs TEMPERATURE FIGURE 48. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD W 43mW SOT3- JA =3 C/W SO8 JA = C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 49. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN74 Rev 3. Page of May 4, 7

13 Pin Descriptions LD SOT-3 8 LD SO PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT VOUT Output V S + V OUT CIRCUIT 4 VS- Supply 3 3 VINA+ Input V S + V IN + V IN - V S - CIRCUIT 4 VINA- Input Reference Circuit 7 VS+ Supply Applications Information Product Description The EL is an ultra-low noise, wideband monolithic operational amplifier built on Elantec's proprietary high speed complementary bipolar process. It features.83nv/ Hz input voltage noise, µv offset voltage, and 73dB THD. It is intended for use in systems such as ultrasound imaging where very small signals are needed to be amplified. The EL also has excellent DC specifications: µv V OS, µa IB,.4µA I OS, and db CMRR. These specifications allow the EL to be used in DC-sensitive applications such as difference amplifiers. Gain-Bandwidth Product The EL has a gain-bandwidth product of 8MHz at ±V. For gains greater than, its closed-loop -3dB bandwidth is approximately equal to the gain-bandwidth product divided by the small signal gain of the circuit. For gains less than, higher-order poles in the amplifier's transfer function contribute to even higher closed-loop bandwidths. For example, the EL has a -3dB bandwidth of 7MHz at a gain of and decreases to 4MHz at gain of. It is important to note that the extra bandwidth at lower gain does not come at the expenses of stability. Even though the EL is designed for gain > with external compensation, the device can also operate at lower gain settings. The RC network shown in Figure reduces the feedback gain at high frequency and thus maintains the amplifier stability. R values must be less than RF divided by 9 and divided by RC must be less than 4MHz. V IN C R FIGURE. Choice of Feedback Resistor, RF The feedback resistor forms a pole with the input capacitance. As this pole becomes larger, phase margin is reduced. This increases ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value which should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few pf range in parallel with RF can help to reduce this ringing and peaking at the expense of reducing the bandwidth. Frequency response curves for various RF values are shown the in typical performance curves section of this data sheet. - + R F V OUT FN74 Rev 3. Page 3 of May 4, 7

14 Noise Calculations The primary application for the EL is to amplify very small signals. To maintain the proper signal-to-noise ratio, it is essential to minimize noise contribution from the amplifier. Figure below shows all the noise sources for all the components around the amplifier. V IN FIGURE. V N is the amplifier input voltage noise I N + is the amplifier positive input current noise I N - is the amplifier negative input current noise V RX is the thermal noise associated with each resistor: V RX = where: R 3 4kTRx V R3 I N + I N - k is Boltzmann's constant =.388 x -3 T is temperature in degrees Kelvin (73+ C) The total noise due to the amplifier seen at the output of the amplifier can be calculated by using the equation below (Figure ). As the equation shows, to keep noise at a minimum, small resistor values should be used. At higher amplifier gain configuration where R is reduced, the noise due to IN-, R, and R decreases and the noise caused by IN+, VN, and R 3 starts to dominate. Because noise is summed in a root-meansquares method, noise sources smaller than % of the largest noise source can be ignored. This can greatly simplify the formula and make noise calculation much easier to calculate. Output Drive Capability The EL is designed to drive low impedance load. It can easily drive V P-P signal into a load. This high output drive capability makes the EL an ideal choice for RF, IF, and video applications. Furthermore, the EL is currentlimited at the output, allowing it to withstand momentary short to ground. However, the power dissipation with output-shorted cannot exceed the power dissipation capability of the package. V N V R R V R + - R V ON Driving Cables and Capacitive Loads Although the EL is designed to drive low impedance load, capacitive loads will decrease the amplifier's phase margin. As shown the in the performance curves, capacitive load can result in peaking, overshoot and possible oscillation. For optimum AC performance, capacitive loads should be reduced as much as possible or isolated with a series resistor between to. When driving coaxial cables, double termination is always recommended for reflection-free performance. When properly terminated, the capacitance of the coaxial cable will not add to the capacitive load seen by the amplifier. Power Supply Bypassing And Printed Circuit Board Layout As with any high frequency devices, good printed circuit board layout is essential for optimum performance. Ground plane construction is highly recommended. Lead lengths should be kept as short as possible. The power supply pins must be closely bypassed to reduce the risk of oscillation. The combination of a 4.7µF tantalum capacitor in parallel with.µf ceramic capacitor has been proven to work well when placed at each supply pin. For single supply operation, where pin 4 (V S -) is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a.µf ceramic capacitor across pins 7 (V S +) and pin 4 (V S -) will suffice. For good AC performance, parasitic capacitance should be kept to a minimum. Ground plane construction again should be used. Small chip resistors are recommended to minimize series inductance. Use of sockets should be avoided since they add parasitic inductance and capacitance which will result in additional peaking and overshoot. Supply Voltage Range and Single Supply Operation The EL has been designed to operate with supply voltage range of ±.V to ±V. With a single supply, the EL will operate from +V to +3V. Pins 4 and 7 are the power supply pins. The positive power supply is connected to pin 7. When used in single supply mode, pin 4 is connected to ground. When used in dual supply mode, the negative power supply is connected to pin 4. As the power supply voltage decreases from +3V to +V, it becomes necessary to pay special attention to the input voltage range. The EL has an input voltage range of.4v from the negative supply to.v from the positive supply. So, for example, on a single +V supply, the EL has an input voltage range which spans from.4v to 3.8V. The output range of the EL is also quite large, on a +V supply, it swings from.4v to 3.V. V ON = BW VN R IN- R R IN+ R 3 R R K T R R + 4 K T R K T R R 3 R R FIGURE. FN74 Rev 3. Page 4 of May 4, 7

15 Small Outline Package Family (SO) A D h X 4 N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE..4 C. M C A B b A DETAIL X L 4 ±4 MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO SO (.3 ) SO SO4 SO8 SYMBOL SO-8 SO-4 (. ) (SOL-) (SOL-) (SOL-4) (SOL-8) TOLERANCE NOTES A MAX - A A b c D , 3 E E , 3 e Basic - L L Basic - h Reference - N Reference - Rev. M /7 NOTES:. Plastic or metal protrusions of. maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994 FN74 Rev 3. Page of May 4, 7

16 SOT-3 Package Family 3. C D X C E SEATING PLANE. C NX e N. C A-B X (L) A e 4 3 B. M C A-B D b NX D 3 H E A D. C X A MDP38 SOT-3 PACKAGE FAMILY MILLIMETERS SYMBOL SOT3- SOT3- TOLERANCE A.4.4 MAX A.. ±. A.4.4 ±. b.4.4 ±. c.4.4 ±. D.9.9 Basic E.8.8 Basic E.. Basic e.9.9 Basic e.9.9 Basic L.4.4 ±. L.. Reference N Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included. 3. This dimension is measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M Index area - Pin # I.D. will be located within the indicated zone (SOT3- only).. SOT3- version has no center lead (shown as a dashed line). A GAUGE PLANE. c L +3 - Copyright Intersil Americas LLC 3-7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN74 Rev 3. Page of May 4, 7