60MHz Rail-to-Rail Input-Output Operational Amplifier

Transcription

1 6MHz Rail-to-Rail Input-Output Operational Amplifier EL52T The EL52T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL52T contains two amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from.5v to 9V. It can be configured for single or dual supply operation, and typically consumes only 3mA per amplifier. The EL52T has an output short circuit capability of ±3mA and a continuous output current capability of ±65mA. The EL52T features a high slew rate of V/μs, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 6MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL52T an ideal amplifier solution for use in TFT-LCD panels as a V COM driver or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL52T is available in a thermally enhanced 8 Ld HMSOP package, and a thermally enhanced 8 Ld DFN package. Both feature a standard operational amplifier pinout. The device operates over an ambient temperature range of - C to +85 C. Features 6MHz (-3dB) Bandwidth.5V to 9V Maximum Supply Voltage Range V/μs Slew Rate 3mA Supply Current (per Amplifier) ±65mA Continuous Output Current ±3mA Output Short Circuit Current Unity-gain Stable Beyond the Rails Input Capability Rail-to-rail Output Swing Built-in Thermal Protection - C to +85 C Ambient Temperature Range Pb-Free (RoHS Compliant) Applications*(see page 3) TFT-LCD Panels V COM Amplifiers Static Gamma Buffers Drivers for A/D Converters Data Acquisition Video Processing Audio Processing Active Filters Test Equipment Battery-powered Applications Portable Equipment EL52T GAIN (db) C L =.5pF R L kω (PROBE) kω 56Ω 5Ω - k M M M FIGURE. TYPICAL TFT-LCD V COM APPLICATION FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS R L May 2, 2 FN6893. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Pin Configuration EL52T (8 LD HMSOP) TOP VIEW EL52T (8 LD DFN) TOP VIEW VS+ VOUTB VINB- VINB+ VOUTA VINA- 2 VINA+ 3 VS PD VOUTA VINA- VINA+ VS- VS+ VOUTB VINB- VINB+ THERMAL PAD IS ELECTRICALLY CONNECTED TO VS- THERMAL PAD IS ELECTRICALLY CONNECTED TO VS- Pin Descriptions PIN NUMBER (HMSOP, DFN) PIN NAME FUNCTION EQUIVALENT CIRCUIT VOUTA Amplifier A output (Reference Circuit ) 2 VINA- Amplifier A inverting input (Reference Circuit 2) 3 VINA+ Amplifier A non-inverting input (Reference Circuit 2) VS- Negative power supply 5 VINB+ Amplifier B non-inverting input (Reference Circuit 2) 6 VINB- Amplifier B inverting input (Reference Circuit 2) 7 VOUTB Amplifier B output (Reference Circuit ) 8 VS+ Positive power supply Pad PD Functions as a heat sink. Electrically connected to VS-. Connect the thermal pad to VS- plane on the PCB for optimum thermal performance. V S+ V S+ V OUTx V INx GND CIRCUIT V S- CIRCUIT 2 V S- Ordering Information PART NUMBER (Notes 2, 3) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # EL52TILZ-T3 (Note ) T 8 Ld DFN L8.2x3 EL52TIYEZ BBBNA 8 Ld HMSOP MDP5 EL52TIYEZ-T7 (Note ) BBBNA 8 Ld HMSOP MDP5 EL52TIYEZ-T3 (Note ) BBBNA 8 Ld HMSOP MDP5 NOTES:. Please refer to TB37 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD For Moisture Sensitivity Level (MSL), please see device information page for EL52T. For more information on MSL please see techbrief TB FN6893. May 2, 2

3 Absolute Maximum Ratings () Supply Voltage between V S + and V S V Input Voltage Range (V INx+, V INx- )... V S - -.5V, V S + +.5V Input Differential Voltage (V INx+ - V INx- ) (V S + +.5V)-(V S - -.5V) Maximum Continuous Output Current ±65mA ESD Rating Human Body Model V Thermal Information Thermal Resistance (Typical) θ JA ( C/W) θ JC ( C/W) 8 Ld HMSOP (Notes, 5) Ld DFN (Notes, 5) Storage Temperature C to +5 C Ambient Operating Temperature C to +85 C Maximum Junction Temperature C Power Dissipation See Figures 3 and 35 Pb-Free Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. θ JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB For θ JC, the case temp location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, to V,, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = V 5 8 mv TCV OS Average Offset Voltage Drift (Note 6) 8 Ld HMSOP package 3 μv/ C 8 Ld DFN package 9 μv/ C I B Input Bias Current V CM = V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V IN from -5.5V to 5.5V 5 73 db A VOL Open-Loop Gain -.5V V OUTx.5V db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA V V OH Output Swing High I L = +5mA V I SC Short-Circuit Current V CM = V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ±3 ma I OUT Output Current ±65 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range.5 9 V I S Supply Current V CM = V, No load ma PSRR Power Supply Rejection Ratio Supply is moved from ±2.25V to ±9.5V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 7) -.V V OUTx.V, 2% to 8% V/μs t S Settling to +.% (Note 8) A V = +, V OUTx = 2V step, 85 ns BW -3dB Bandwidth, C L =.5pF 6 MHz 3 FN6893. May 2, 2

4 Electrical Specifications V S + = +5V, V S - = -5V, to V,, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT GBWP Gain-Bandwidth Product A V = -, R F = kω, R G = Ω PM Phase Margin A V = -, R F = kω, R G = Ω 32 MHz 5 CS Channel Separation f = 5MHz 9 db Electrical Specifications V S + = +5V, V S - = V, to 2.5V,, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 2.5V 5 8 mv TCV OS Average Offset Voltage Drift (Note 6) 8 Ld HMSOP package μv/ C 8 Ld DFN package 8 μv/ C I B Input Bias Current V CM = 2.5V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V IN from -.5V to 5.5V 5 68 db A VOL Open-Loop Gain.5V V OUTx.5V db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -.2mA 6 5 mv V OH Output Swing High I L = +.2mA.85.9 V I SC Short-circuit Current V CM = 2.5V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ± ma I OUT Output Current ±65 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range.5 9 V I S Supply Current V CM = 2.5V, No load ma PSRR Power Supply Rejection Ratio Supply is moved from.5v to 9V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 7) V V OUTx V, 2% to 8% 75 V/μs t S Settling to +.% (Note 8) A V = +, V OUTx = 2V step, 9 ns BW -3dB Bandwidth, C L =.5pF 6 MHz GBWP Gain-Bandwidth Product A V = -, R F = kω, R G = Ω PM Phase Margin A V = -, R F = kω, R G = Ω 32 MHz 5 CS Channel Separation f = 5MHz 9 db FN6893. May 2, 2

5 Electrical Specifications V S + = +8V, V S - = V, to 9V,, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 9V 7 8 mv TCV OS Average Offset Voltage Drift (Note 6) 8 Ld HMSOP package μv/ C 8 Ld DFN package μv/ C I B Input Bias Current V CM = 9V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V IN from -.5V to 8.5V db A VOL Open-Loop Gain.5V V OUTx 7.5V 62 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -6mA 8 5 mv V OH Output Swing High I L = +6mA V I SC Short-circuit Current V CM = 9V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ±3 ma I OUT Output Current ±65 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range.5 9 V I S Supply Current V CM = 9V, No load ma PSRR Power Supply Rejection Ratio Supply is moved from.5v to 9V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 7) V V OUTx 7V, 2% to 8% V/μs t S Settling to +.% (Note 8) A V = +, V OUTx = 2V step, ns BW -3dB Bandwidth, C L =.5pF 6 MHz GBWP Gain-Bandwidth Product A V = -, R F = kω, R G = Ω PM Phase Margin A V = -, R F = kω, R G = Ω 32 MHz 5 CS Channel Separation f = 5MHz 9 db NOTES: 6. Measured over - C to +85 C ambient operating temperature range. See the typical TCV OS production distribution shown in the Typical Performance Curves on page Typical slew rate is an average of the slew rates measured on the rising (2% to 8%) and the falling (8% to 2%) edges of the output signal. 8. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a ±.% error band. The range of the error band is determined by: Final Value(V) ± [Full Scale(V) *.%]. 5 FN6893. May 2, 2

6 Typical Performance Curves QUANTITY (AMPLIFIERS) TYPICAL PRODUCTION DISTRIBUTION QUANTITY (AMPLIFIERS) C to +85 C TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE DRIFT ( μv / C) FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE. INPUT OFFSET VOLTAGE DRIFT (HMSOP) QUANTITY (AMPLIFIERS) C to +85 C TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE DRIFT ( μv / C) TEMPERATURE ( C) FIGURE 5. INPUT OFFSET VOLTAGE DRIFT (DFN) FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE INPUT BIAS CURRENT (na) 3 2 OUTPUT HIGH VOLTAGE (V) I OUT = +5mA TEMPERATURE ( C) FIGURE 7. INPUT BIAS CURRENT vs TEMPERATURE TEMPERATURE ( C) FIGURE 8. OUTPUT HIGH VOLTAGE vs TEMPERATURE 6 FN6893. May 2, 2

7 Typical Performance Curves (Continued) OUTPUT HIGH VOLTAGE (V) I OUT = -5mA OPEN LOOP GAIN (db) TEMPERATURE ( C) FIGURE 9. OUTPUT LOW VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE. OPEN-LOOP GAIN vs TEMPERATURE SLEW RATE (V/μs) SUPPLY CURRENT (ma) NO LOAD INPUT AT GND TEMPERATURE ( C) FIGURE. SLEW RATE vs TEMPERATURE TEMPERATURE ( C) FIGURE 2. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE SUPPLY CURRENT (ma) NO LOAD INPUT AT GND SUPPLY VOLTAGE (±V) FIGURE 3. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE SLEW RATE (V/μs) C L = 8pF SUPPLY VOLTAGE (±V) FIGURE. SLEW RATE vs SUPPLY VOLTAGE 7 FN6893. May 2, 2

8 Typical Performance Curves (Continued) OPEN LOOP GAIN (db) OPEN LOOP GAIN (db) GAIN R F = 5kΩ, R G = Ω C L = 8pF PHASE PHASE ( ) SUPPLY VOLTAGE (±V) FIGURE 5. OPEN LOOP GAIN vs SUPPLY VOLTAGE -2 - k k k M M M FIGURE 6. OPEN LOOP GAIN AND PHASE OPEN LOOP GAIN (db) GAIN PHASE R F = kω, R G = Ω kω (PROBE) C L =.5pF -2 - k k k M M M FIGURE 7. OPEN LOOP GAIN AND PHASE PHASE ( ) GAIN (db) C L =.5pF R L kω (PROBE) kω 56Ω 5Ω - k M M M FIGURE 8. FREQUENCY RESPONSE FOR VARIOUS R L GAIN (db) pf pf 7pF pf -2 k M M M FIGURE 9. FREQUENCY RESPONSE FOR VARIOUS C L OUTPUT IMPEDANCE (Ω) R F = 2kΩ R L = 5Ω SOURCE = dbm. k k k M M M FIGURE 2. CLOSED LOOP OUTPUT IMPEDANCE 8 FN6893. May 2, 2

9 Typical Performance Curves (Continued) MAXIMUM OUTPUT SWING (V P-P ) DISTORTION <% k k M M M FIGURE 2. MAXIMUM OUTPUT SWING vs FREQUENCY DISTORTION (dbc) nd HD 3rd HD A V = 2 f IN = MHz OUTPUT VOLTAGE (V OP-P ) FIGURE 22. HARMONIC DISTORTION vs V OP-P CMRR (db) V INx = -dbm -9 k k k E+6 E+7 E+8 FIGURE 23. CMRR PSRR (db) PSRR+ PSRR- -8 k k k E+6 E+7 E+8 FIGURE 2. PSRR VOLTAGE NOISE (nv/ Hz) CROSSTALK (db) V INx = dbm k k k M M M FIGURE 25. INPUT VOLTAGE NOISE SPECTRAL DENSITY -2 k k M M M FIGURE 26. CHANNEL SEPARATION 9 FN6893. May 2, 2

10 Typical Performance Curves (Continued) OVERSHOOT (%) V INx = ±5mV k LOAD CAPACITANCE (pf) FIGURE 27. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE STEP SIZE (V) kω (PROBE) C L =.5pF SETTLING TIME (ns) FIGURE 28. STEP SIZE vs SETTLING TIME V/DIV 5mV/DIV 6V STEP kω (PROBE) C L =.5pF mv STEP kω (PROBE) C L =.5pF 5ns/DIV 5ns/DIV FIGURE 29. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 3. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 3. BASIC TEST CIRCUIT FN6893. May 2, 2

11 Applications Information Product Description The EL52T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL52T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The EL52T features a high slew rate of V/μs, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 6MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. Operating Voltage, Input and Output Capability The EL52T can operate on a single supply or dual supply configuration. The EL52T operating voltage ranges from a minimum of.5v to a maximum of 9V. This range allows for a standard 5V (or ±2.5V) supply voltage to dip to -%, or a standard 8V (or ±9V) to rise by +5.5% without affecting performance or reliability. The input common-mode voltage range of the EL52T extends 5mV beyond the supply rails. Also, the EL52T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than.5v, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 32 shows the input voltage driven 5mV beyond the supply rails and the device output swinging between the supply rails. The EL52T output typically swings to within 5mV of positive and negative supply rails with load currents of ±5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 33 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from ±5V supply with a kω load connected to GND. The input is a V P-P sinusoid and the output voltage is approximately 9.9V P-P. Refer to the Electrical Specifications Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the Typical Performance Curves on page 6. Output Current The EL52T is capable of output short circuit currents of 3mA (source and sink), and the device has built-in protection circuitry which limits the output current to ±3mA (typical). V/DIV FIGURE 32. OPERATION WITH BEYOND-THE-RAILS INPUT 5V/DIV V S = ±2.5V,,, V INx = 6V P-P, to GND INPUT OUTPUT μs/div,,, V INx = V P-P, to GND μs/div FIGURE 33. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT To maintain maximum reliability, the continuous output current should never exceed ±65mA. This ±65mA limit is determined by the characteristics of the internal metal interconnects. Also, see Power Dissipation on page 2 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. Unused Amplifiers It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground. Thermal Shutdown The EL52T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +65 C (typical), the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by +5 C (typical), the device automatically turns ON the outputs by putting them in a low impedance (normal) operating state. INPUT OUTPUT FN6893. May 2, 2

12 Driving Capacitive Loads As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL52T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL52T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between Ω to Ω). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. Power Dissipation With the high-output drive capability of the EL52T amplifiers, it is possible to exceed the +5 C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL52T in the application. Proper load conditions will ensure that the EL52T junction temperature stays within a safe operating region. The maximum power dissipation allowed in a package is determined according to Equation : T P JMAX T AMAX DMAX = θ JA where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature Θ JA = Thermal resistance of the package P DMAX = Maximum power dissipation allowed The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or: when sourcing, and: when sinking, where: i = to 2 (, 2 corresponds to Channel A, B respectively) V S = Total supply voltage (V S + - V S -) V S + = Positive supply voltage (EQ. ) P = DMAX ΣiV [ S I SMAX + ( VS + V OUT i ) I LOAD i ] (EQ. 2) P = DMAX ΣiV [ S I SMAX + ( VOUT i V S - ) I LOAD i ] (EQ. 3) V S - = Negative supply voltage I SMAX = Maximum supply current per amplifier (I SMAX = EL52T quiescent current 2) V OUT = Output voltage I LOAD = Load current Device overheating can be avoided by calculating the minimum resistive load condition, R LOAD, resulting in the highest power dissipation. To find R LOAD set the two P DMAX equations equal to each other and solve for V OUT /I LOAD. Reference the package power dissipation curves, Figures 3 and 35, for further information. POWER DISSIPATION (W) JEDEC JESD5-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 78mW 69mW HMSOP8 θ JA = +8 C/W DFN8 θ JA = +6 C/W AMBIENT TEMPERATURE ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (-LAYER) TEST BOARD - EXPOSED DIEPAD SOLDERED TO PCB PER JESD W 2.2W HMSOP8 θ JA = +62 C/W DFN8 θ JA = +58 C/W AMBIENT TEMPERATURE ( C) FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Power Supply Bypassing and Printed Circuit Board Layout The EL52T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as 2 FN6893. May 2, 2

13 possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the V S - pin is connected to ground) a.7μf capacitor should be placed from V S + to ground, then a parallel.μf capacitor should be connected as close to the amplifier as possible. One.7μF capacitor may be used for multiple devices. For dual supply operation, the same capacitor combination should be placed at each supply pin to ground. It is highly recommended that EL52T exposed thermal pad packages should always have the pad connected to the lowest potential, V S -, to optimize thermal and operating performance. PCB vias should be placed below the device s exposed thermal pad to transfer heat to the V S - plane and away from the device. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 5/2/ FN6893. Initial Release. 2/2/ FN6893. Pre-release data sheet submitted for formatting. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: EL52T To report errors or suggestions for this datasheet, please go to FITs are available from our website at 3 FN6893. May 2, 2

14 Package Outline Drawing L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev, 3/ 2. A B PIN INDEX AREA 6 PIN # INDEX AREA 2X.5 6X / (X).5 TOP VIEW 8X. ± /-.5 8X /-.5. M C A B BOTTOM VIEW SEE DETAIL "X".9 ±. (.65) (.5) (8X.6).5 MAX SIDE VIEW. C C BASE PLANE SEATING PLANE.8 C (2.8)(.8).2 REF C (6X.5) (8X.25) TYPICAL RECOMMENDED LAND PATTERN NOTES:.5 MAX DETAIL "X" Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y.5m-99. Unless otherwise specified, tolerance : Decimal ±.5 Dimension applies to the metallized terminal and is measured between.25mm and.3mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. Compies to JEDEC MO-229 VCED-2. FN6893. May 2, 2

15 HMSOP (Heat-Sink MSOP) Package Family E.25 M C A B B E N MDP5 HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY SYMBOL MILLIMETERS HMSOP8 HMSOP TOLERANCE NOTES D (N/2)+ A.. Max. - A /-.5 - A ±.9 - (N/2) PIN # I.D. TOP VIEW A b /-.8 - c.5.5 ±.5 - D ±., 3 EXPOSED THERMAL PAD E2 D Reference - E.9.9 ±.5 - E ±. 2, 3 D E Reference - e.65.5 Basic - L ±.5 - L Basic - BOTTOM VIEW N 8 Reference - C SEATING PLANE. C N LEADS e b SIDE VIEW H.8 M C A B Rev. 2/7 NOTES:. Plastic or metal protrusions of.5mm maximum per side are not included. 2. Plastic interlead protrusions of.25mm maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99. L A c END VIEW SEE DETAIL "X".25 GAUGE PLANE A2 3 ±3 L DETAIL X A For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 5 FN6893. May 2, 2

16 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Intersil: EL52TILZ-T3 EL52TIYEZ EL52TIYEZ-T3 EL52TIYEZ-T7