CA3140, CA3140A. 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output. Description. Features. Applications. Ordering Information

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1 November 99 SEMICONDUCTOR CA, CAA.MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output Features MOSFET Input Stage - Very High Input Impedance (Z IN ) -.TΩ (Typ) - Very Low Input Current (I l ) -pa (Typ) at ±V - Wide Common Mode Input Voltage Range (V lcr ) - Can be Swung.V Below Negative Supply Voltage Rail - Output Swing Complements Input Common Mode Range Directly Replaces Industry Type in Most Applications Applications Ground-Referenced Single Supply Amplifiers in Automobile and Portable Instrumentation Sample and Hold Amplifiers Long Duration Timers/Multivibrators (µseconds-minutes-hours) Photocurrent Instrumentation Peak Detectors Active Filters Comparators Interface in V TTL Systems and Other Low Supply Voltage Systems All Standard Operational Amplifier Applications Function Generators Tone Controls Power Supplies Portable Instruments Intrusion Alarm Systems Description The CAA and CA are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip. The CAA and CA BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CAA and CA operate at supply voltage from V to V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to.v below the negative supply terminal, an important attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. The CA Series has the same 8-lead pinout used for the and other industry standard op amps. The CAA and CA are intended for operation at supply voltages up to V (±8V). Ordering Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PKG. NO. PACKAGE CAAE - to 8 Ld PDIP E8. CAAM - to 8 Ld SOIC M8. (A) CAAS - to 8 Pin Metal Can T8.C CAAT - to 8 Pin Metal Can T8.C CAE - to 8 Ld PDIP E8. CAM () - to 8 Ld SOIC M8. CAM9 () - to 8 Ld SOIC Tape and Reel CAT - to 8 Pin Metal Can T8.C Pinouts CA (METAL CAN) TOP VIEW CA (PDIP, SOIC) TOP VIEW INV. NON-INV. TAB 8 - V V- AND CASE INV. NON-INV. V- - 8 V CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 99-9 File Number 9.

2 CA, CAA Absolute Maximum Ratings DC Supply Voltage (Between V and V- Terminals) V Differential Mode Input Voltage V DC Input Voltage (V 8V) To (V- -.V) Input Terminal Current ma Output Short Circuit Duration (Note ) Indefinite Operating Conditions Temperature Range o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A SOIC Package N/A Metal Can Package Maximum Junction Temperature (Metal Can Package) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. θ JA is measured with the component mounted on an evaluation PC board in free air.. Short circuit may be applied to ground or to either supply. V SUPPLY = ±V, T A = o C PARAMETER SYMBOL TEST CONDITIONS Input Offset Voltage Adjustment Resistor Typical Value of Resistor Between Terminals and or and to Adjust Max V IO TYPICAL VALUES CA CAA UNITS. 8 kω Input Resistance R I.. TΩ Input Capacitance C I pf Output Resistance R O Ω Equivalent Wideband Input Noise Voltage, (See Figure ) e N BW = khz, R S = MΩ 8 8 µv Equivalent Input Noise Voltage (See Figure ) e N R S = Ω f = khz nv/ Hz f = khz nv/ Hz Short Circuit Current to Opposite Supply I OM Source ma I OM - Sink 8 8 ma Gain-Bandwidth Product, (See Figures, ) f T.. MHz Slew Rate, (See Figure ) SR 9 9 V/µs Sink Current From Terminal 8 To Terminal to Swing Output Low µa Transient Response (See Figure 8) t r R L = kω Rise Time.8.8 µs OS C L = pf Overshoot % Settling Time at V P-P, (See Figure ) t S R L = kω To mv.. µs C L = pf Voltage Follower To mv.. µs For Equipment Design, at V SUPPLY = ±V, T A = o C, Unless Otherwise Specified CA CAA PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage V IO - - mv Input Offset Current I IO pa Input Current I I - - pa Large Signal Voltage Gain (Note ) A OL - - kv/v (See Figures, 9) db Common Mode Rejection Ratio CMRR - - µv/v (See Figure ) db Common Mode Input Voltage Range (See Figure 8) V ICR - -. to to. V -8

3 CA, CAA For Equipment Design, at V SUPPLY = ±V, T A = o C, Unless Otherwise Specified (Continued) PARAMETER Power-Supply Rejection Ratio, V IO / V S (See Figure ) SYMBOL CA CAA MIN TYP MAX MIN TYP MAX PSRR - - µv/v db Max Output Voltage (Note ) V OM - - V (See Figures, 8) V OM V Supply Current (See Figure ) I - - ma Device Dissipation P D mw Input Offset Voltage Temperature Drift V IO / T µv/ o C NOTES:. At V O = V P-P, V, -V and R L = kω.. At R L = kω. UNITS For Design Guidance At V = V, V- = V, T A = o C TYPICAL VALUES PARAMETER SYMBOL CA CAA UNITS Input Offset Voltage V IO mv Input Offset Current I IO.. pa Input Current I I pa Input Resistance R I TΩ Large Signal Voltage Gain (See Figures, 9) A OL kv/v db Common Mode Rejection Ratio CMRR µv/v 9 9 db Common Mode Input Voltage Range (See Figure 8) V ICR V.. V Power Supply Rejection Ratio PSRR µv/v V I / V S 8 8 db Maximum Output Voltage (See Figures, 8) V OM V V OM -.. V Maximum Output Current: Source I OM ma Sink I OM - ma Slew Rate (See Figure ) SR V/µs Gain-Bandwidth Product (See Figure ) f T.. MHz Supply Current (See Figure ) I.. ma Device Dissipation P D 8 8 mw Sink Current from Terminal 8 to Terminal to Swing Output Low µa -8

4 CA, CAA Block Diagram ma ma V BIAS CIRCUIT CURRENT SOURCES AND REGULATOR - A µa.ma µa µa ma A, C A pf V- 8 Schematic Diagram BIAS CIRCUIT STAGE SECOND STAGE STAGE DYNAMIC CURRENT SINK V Q D Q Q D R 9 Ω Q R K Q Q Q Q Q 9 R K R Ω R K D 8 R K R 8K Q 8 Q R 8 Q K Q 8 D D D D INVERTING NON-INVERTING - Q 9 Q C R Ω R Ω Q Q pf Q Q Q Q D R Ω R Ω R Ω R Ω 8 V- NOTE: All resistance values are in ohms. -8

5 CA, CAA Typical Performance Curves OPEN-LOOP VOLTAGE GAIN (db) R L = kω o C o C GAIN BANDWIDTH PRODUCT (MHz) R L = kω C L = pf o C o C FIGURE 9. OPEN-LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE AND TEMPERATURE FIGURE. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE AND TEMPERATURE SLEW RATE (V/µs) R L = kω C L = pf o C o C QUIESCENT SUPPLY CURRENT (ma) R L = o C o C FIGURE. SLEW RATE vs SUPPLY VOLTAGE AND TEMPERATURE FIGURE. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE AND TEMPERATURE SWING (V P-P ) SUPPLY VOLTAGE: V S = ±V T A = o C COMMON-MODE REJECTION RATIO (db) 8 SUPPLY VOLTAGE: V S = ±V T A = o C CAB CA, CAA K K M M FIGURE. MAXIMUM VOLTAGE SWING vs FREQUENCY FIGURE. COMMON MODE REJECTION RATIO vs FREQUENCY -9

6 CA, CAA Typical Performance Curves (Continued) EQUIVALENT NOISE VOLTAGE (nv Hz) SUPPLY VOLTAGE: V S = ±V T A = o C FIGURE. EQUIVALENT NOISE VOLTAGE vs FREQUENCY POWER SUPPLY REJECTION RATIO (db) 8 SUPPLY VOLTAGE: V S = ±V T A = o C CAB CA CAA -PSRR POWER SUPPLY REJECTION RATIO (PSRR) = V IO / V S PSRR FIGURE. POWER SUPPLY REJECTION RATIO vs FREQUENCY Metallization Mask Layout 8- (.-.) - (.-.) - (.-.8) Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( - inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are o instead of 9 ο with respect to the face of the chip. Therefore, the isolated chip is actually mils (.mm) larger in both dimensions. -9