CA3290, CA3290A. BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output. Features. Applications. Pinout. Ordering Information

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1 Data Sheet September 99 File Number 09.3 BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output The CA390A and CA390 types consist of a dual voltage comparator on a single monolithic chip. The common mode input voltage range includes ground even when operated from a single supply. The low supply current drain makes these comparators suitable for battery operation; their extremely low input currents allow their use in applications that employ sensors with extremely high source impedances. Package options are shown in the table below. Pinout OUTPUT (A ) INV. (A ) NON-INV. (A ) 3 A CA390/A (PDIP) TOP VIEW A 7 5 V+ OUTPUT (A ) INV. (A ) NON-INV. (A ) Features MOSFET Input Stage - Very High Input Impedance (Z IN ) TΩ (Typ) - Very Low Input Current at V+ = 5V pA (Typ) - Wide Common Mode Input Voltage Range (V ICR ) Can Be Swung.5V (Typ) Below Negative Supply Voltage Rail - Virtually Eliminates Errors Due to Flow of Input Currents Output Voltage Compatible with TTL, DTL, ECL, MOS, and CMOS Logic Systems in Most Applications Applications High Source Impedance Voltage Comparators Long Time Delay Circuits Square Wave Generators A/D Converters Window Comparators Ordering Information PART NUMBER TEMP RANGE ( o C) PACKAGE PKG. NO. CA390AE -55 to 5 Ld PDIP E.3 CA390E -55 to 5 Ld PDIP E.3 Schematic Diagram (ONLY ONE IS SHOWN) COMPARATOR NO. BIASING CIRCUIT FOR CURRENT SOURCES V+ TO COMP. NO. I I I 3 I Q9 Q0 50µA 00µA 50µA Q 00µA Q V O Q 3 Q D D 3 D Q Q 3 D Q Q 5 Q Q Q Q 7 Q +V I -V I Q 7 R 00kΩ R kω Q 5 Q R 3 5kΩ C 5pF CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --INTERSIL or Copyright Intersil Corporation 999

2 Absolute Maximum Ratings Supply Voltage Single Supply V Dual Supply ±V Differential Input Voltage V or [(V+ - ) +5V] (whichever is less) DC Input Voltage V+ +5V to -5V Output to Short Circuit Duration (Note ) Continuous Input Current ma Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C Operating Conditions Temperature Range to 5 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TEMP ( o C) CA390A CA390 MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage V IO V CM = V O =.V, V+ = 5V Full mv V CM = V O = 0V, V+ = +5V, = -5V Full mv V CM = V O =.V, V+ = 5V mv V CM = V O = 0V, V+ = +5V, = -5V mv Temperature Coefficient of Input Offset Voltage V IO / T µv/ o C Input Offset Current I IO V CM =.V, V+ = 5V Full na V CM = 0V, V+ = +5V, = -5V Full na V CM =.V, V+ = 5V pa V CM = 0V, V+ = +5V, = -5V pa Input Current I I V CM =.V, V+ = 5V na V CM = 0V, V+ = +5V, = -5V na V CM =.V, V+ = 5V pa V CM = 0V, V+ = +5V, = -5V pa Supply Current I+ R L =, V+ = 5V ma R L =, V+ = 30V ma R L =, V+ = 5V ma R L =, V+ = 30V ma Voltage Gain A OL R L = 5kΩ, V+ = +5V, = -5V R L = 5kΩ, V+ = +5V, = -5V Full V/mV db V/mV - - db

Electrical Specifications = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP ( o C) CA390A CA390 MIN TYP MAX MIN TYP MAX UNITS Saturation Voltage V SAT I SINK = ma, V+

3 Electrical Specifications = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP ( o C) CA390A CA390 MIN TYP MAX MIN TYP MAX UNITS Saturation Voltage V SAT I SINK = ma, V+ = 5V, +V I = 0V, -V I = V I SINK = ma, V+ = 5V, +V I = 0V, -V I = V I SINK = ma, V+ = 5V, +V I = 0V, -V I = V V V V Output Leakage Current I OL V+ = 5V Full na V+ = 3V Full - 30 k - 30 k na V+ = 5V pa V+ = 3V pa Common Mode Input Voltage Range V ICR V O =.V, V+ = 5V 5 V V V V V V O = 0V, V+ = +5V, = -5V 5 V+ -3. V V+ -3. V V Common Mode Rejection Ratio Power Supply Rejection Ratio CMRR V+ = +5V, = -5V µv/v V+ = 5V µv/v PSRR V+ = +5V, = -5V µv/v Output Sink Current V O =.V, V+ = 5V ma Response Time Rising Edge Response Time Falling Edge Large Signal Response Time t r R L = 5.kΩ, V+ = 5V µs t f R L = 5.kΩ, V+ = 5V ns R L = 5.kΩ, V+ = 5V ns R L = 5.kΩ, V+ = 5V ns Test Circuits and Waveforms C C = pf +5V +5V V IN K + - TO 0X SCOPE PROBE K -5V WITH C C Top Trace.5mV/Div. = V IN Bottom Trace = 0V/Div. = V OUT Time Scale = 5µs/Div. FIGURE. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS WITHOUT C C Top Trace.5mV/Div. Bottom Trace = 0V/Div. Time Scale = 5µs/Div. 3

Test Circuits and Waveforms +5V GND GND K K + - 5.K OUTPUT 00mV 0mV 5mV 5mV 0mV 00mV FIGURE. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS +5V GND GND K 5.

INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS Circuit Description The Basic Comparator Figure shows the basic circuit diagram for one of the two comparators in the CA390.

Transistors Q through Q comprise the differential input stage, with Q 5 and Q serving as a mirror connected active load and differential-to-single-ended converter.

For example, if +V IN is greater than -V IN,Q,Q, and current mirror transistors Q 5 and Q will be turned off; Transistors Q 3, Q, and Q 7 will be turned on, causing Q to be turned off.

4 Test Circuits and Waveforms +5V GND GND K K K OUTPUT 00mV 0mV 5mV 5mV 0mV 00mV FIGURE. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS +5V GND GND K 5.K + - OUTPUT K 5mV 0mV 00mV 00mV 0mV 5mV FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS Circuit Description The Basic Comparator Figure shows the basic circuit diagram for one of the two comparators in the CA390. It is generically similar to the industry type 39 comparators, with PMOS transistors replacing PNP transistors as input stage elements. Transistors Q through Q comprise the differential input stage, with Q 5 and Q serving as a mirror connected active load and differential-to-single-ended converter. The differential input at Q and Q is amplified so as to toggle Q in accordance with the input signal polarity. For example, if +V IN is greater than -V IN,Q,Q, and current mirror transistors Q 5 and Q will be turned off; Transistors Q 3, Q, and Q 7 will be turned on, causing Q to be turned off. The output is pulled positive when a load resistor is connected between the output and V+. In essence, Q and Q function as source followers to drive Q and Q 3, respectively, with zener diodes D through D providing gate oxide protection against input voltage transients (e.g., static electricity). The current flow in Q and Q is established at approximately 50µA by constant current sources I and I 3, respectively. Since Q and Q are operated with a constant current load, their gate-to-source voltage drops will be effectively constant as long as the input voltages are within the common-mode range. As a result, the input offset voltage (V GS(Q) + V BE(Q) - V BE(Q3) - V GS(Q) ) will not be degraded when a large differential DC voltage is applied to the device for extended periods of time at high temperatures. Additional voltage gain following the first stage is provided by transistors Q 7 and Q. The collector of Q is open, offering the user a wide variety of options in applications. An additional discrete transistor can be added if it becomes necessary to boost the output sink current capability. The detailed schematic diagram for one comparator and the common current source biasing is shown on the front page. PMOS transistors Q 9 through Q are the current source elements identified in Figure as I through I, respectively.

5 Their gate source potentials (V GS ) are supplied by a common bus from the biasing circuit shown in the right hand portion of the Schematic Diagram. The currents supplied by Q 0 and Q are twice those supplied by Q 9 and Q. The transistor geometries are appropriately scaled to provide the requisite currents with common V GS applied to Q 9 through Q. V I + D D V+ I 50µA Q P Q Q 5 Q 3 I 00µA Operating Considerations Input Circuit The use of MOS transistors in the input stage of the CA390 series circuits provides the user with the following features for comparator applications:. Ultra high input impedance (.7TΩ);. The availability of common mode rejection for input signals at potentials below that of the negative power supply rail; 3. Retention of the in phase relationship of the input and output signals for input signals below the negative rail. Although the CA390 employs rugged bipolar (zener) diodes for protection of the input circuit, the input terminal currents should not exceed ma. Appropriate series connected limiting resistors should be used in circuits where greater current flows might exist, allowing the signal input voltage to be greater than the supply voltage without damaging the circuit. Output Circuit The output of the CA390 is the open collector of an n-p-n transistor, a feature providing flexibility in a broad range of comparator applications. An output ORing function can be implemented by parallel connection of the open collectors. An output pull-up resistor can be connected to a power supply having a voltage range within the rating of the particular CA390 in use; the magnitude of this voltage may be set at a value which is independent of that applied to the V+ terminal of the CA390. Parasitic Oscillations The ideal comparator has, among other features, ultra high input impedance, high gain, and wide bandwidth. These desirable characteristics may, however, produce parasitic oscillations unless certain precautions are observed to Q I 3 50µA V I - I 00µA D 3 D V O Q P FIGURE. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO COMPARATORS Q7 Q minimize the stray capacitive coupling between the input and output terminals. Parasitic oscillations manifest themselves during the output voltage transition intervals as the comparator switches states. For high source impedances, stray capacitance can induce parasitic oscillations. The addition of a small amount (mv to 0mV) of positive feedback (hysteresis) produces a faster transition, thereby reducing the likelihood of parasitic oscillations. Furthermore, if the input signal is a pulse waveform, with relatively rapid rise and fall times, parasitic tendencies are reduced. When dual comparators, like the CA390, are packaged in an lead configuration, the output terminal of each comparator is adjacent to an input terminal. The lead-to-lead capacitance is approximately pf, which may be sufficient to cause undesirable feedback effects in certain applications. Circuit factors such as impedance levels, supply voltage, switching rate, etc., may increase the possibility of parasitic oscillations. To minimize this potential oscillatory condition, it is recommended that for source impedances greater than kω a capacitor ( pf - pf) be connected between the appropriate input terminal and the output terminal. (See Figure.) If either comparator is unused, its input terminals should also be tied to either the V+ or supply rail. Typical Applications Light Controlled One-Shot Timer In Figure 5 one comparator (A ) of the CA390 is used to sense a change in photo diode current. The other comparator (A ) is configured as a one-shot timer and is triggered by the output of A. The output of the circuit will switch to a low state for approximately 0 seconds after the light source to the photo diode has been interrupted. The circuit operates at normal room lighting levels. The sensitivity of the circuit may be adjusted by changing the values of R and R. The ratio of R to R should be constant to insure constant reverse voltage bias on the photo diode. R.5MΩ R MΩ +5V 5kΩ 5 kω +5V MΩ +5V N9 0MΩ 3 + 0kΩ A CA390 +5V - C µF N9.0µF 3.3kΩ +5V 5 + A CA kΩ X 0s TIME FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER 5

6 Low-Frequency Multivibrator In this application, one half of the CA390 is used as a conventional multivibrator circuit. Because of the extremely high input impedance of this device, large values of timing resistor (R ) may be used for long time delays with relatively small leakage timing capacitors. The second half of the CA390 is used as an output buffer to insure that the multivibrator frequency will not be affected by output loading. R P is the parallel combination of the two MΩ resistors connected between +5V and GND. MΩ R P MΩ +5V R 0MΩ C 0.3 µf 3 +5V - A CA390 + R MΩ 5kΩ +5V MΩ 5 MΩ 3.3kΩ +5V + A CA t = Period = 0s R P t = R Clog e R Window Comparator Both halves of the CA390 can be used in a high input impedance window comparator as shown in Figure 7. The LED will be turned on whenever the input signal is above the lower limit (V L ) but below the upper limit (V U ), as determined by the R /R /R 3 resistor divider. +5V 00kΩ R 7kΩ R 7kΩ V L 00kΩ A - - CA kΩ A CA390 V U 3 + R 3.kΩ 5 +5V FIGURE 7. WINDOW COMPARATOR 7 LED 70Ω N0 FIGURE. LOW FREQUENCY MULTIVIBRATOR Typical Performance Curves R L = 0 T A = 5 o C V+ = +30V, = GND SUPPLY CURRENT (ma) o C 5 o C CURRENT (pa) TOTAL SUPPLY VOLTAGE (V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE (BOTH AMPLIFIERS) COMMON MODE VOLTAGE (V) FIGURE 9. CURRENT vs COMMON MODE VOLTAGE

7 Typical Performance Curves (Continued) CURRENT (pa) T A = 5 o C V+ = +5V, = GND EXCURSIONS FROM V+ TERMINAL (V) o C 5 o C COMMON MODE VOLTAGE (V) POSITIVE SUPPLY VOLTAGE (V) FIGURE 0. CURRENT vs COMMON MODE VOLTAGE FIGURE. POSITIVE COMMON MODE VOLTAGE RANGE vs SUPPLY VOLTAGE EXCURSIONS FROM TERMINAL (V) o C 5 o C NEGATIVE SUPPLY VOLTAGE (V) CURRENT (pa) 0K K 00 0 V+ = +5V, = -5V V CM = 0V TEMPERATURE ( o C) V+ = 5V, = 0V V CM =.V FIGURE. NEGATIVE COMMON MODE VOLTAGE RANGE vs SUPPLY VOLTAGE FIGURE 3. CURRENT vs TEMPERATURE OUTPUT SATURATION VOLTAGE 0V V 00mV 0mV 5 o C 5 o C 5 o C 5 o C mv 0µA 00µA ma 0mA OUTPUT SINK CURRENT FIGURE. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT 7

Metallization Mask Layout 90 0 0 0 30 0 5053 0 7 0 70 0 50 0 30 0 7-95 (.0 -.03) The photographs and dimensions of each chip represent a chip when it is part of the wafer.

8 Metallization Mask Layout ( ) The photographs and dimensions of each chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57 o instead of 90 o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.7mm) larger in both dimensions. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (0-3 inch) NOTE: Numbers in pads are for lead DIP and TO-5 Can and numbers outside of chip are for lead DIP ( ) 50-5 ( ) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 3, Mail Stop 53-0 Melbourne, FL 390 TEL: (3) FAX: (3) 7-70 EUROPE Intersil SA Mercure Center 00, Rue de la Fusee 30 Brussels, Belgium TEL: (3).7. FAX: (3) ASIA Intersil (Taiwan) Ltd. 7F-, No. 0 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: () FAX: ()

CA5260, CA5260A. 3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output. Features. Description.

CA5260, CA5260A. 3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output. Features. Description. , A November 1996 3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output Features Description MOSFET Input Stage provides - Very High Z I = 1.5TΩ (1.5 x 10 12 Ω) (Typ) - Very Low