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2 IRF8 Data Sheet July 999 File Number 8..A, V,. Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA7. Ordering Information PART NUMBER PACKAGE BRAND Features.A, V r DS(ON) =.Ω Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB Guidelines for Soldering Surface Mount Components to PC Boards Symbol D IRF8 TO-AB IRF8 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-AB SOURCE DRAIN GATE DRAIN (FLANGE) - CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. or Copyright Intersil Corporation 999

3 IRF8 Absolute Maximum Ratings T C = o C, Unless Otherwise Specified IRF8 UNITS Drain to Source Voltage (Note ) V Drain to Gate Voltage (R GS = kω) (Note ) V DGR V Continuous Drain Current I D. A T C = o C I D. A Pulsed Drain Current (Note ) I DM 8 A Gate to Source Voltage V GS ± V Maximum Power Dissipation P D 7 W Linear Derating Factor W/ o C Single Pulse Avalanche Energy Rating (Note ) E AS mj Operating and Storage Temperature T J,T STG - to o C Maximum Temperature for Soldering Leads at.6in (.6mm) from Case for s T L Package Body for s, See Techbrief T pkg 6 o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. T J = o C to o C. Electrical Specifications T C = o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BS V GS = V, I D = µa (Figure ) - - V Gate to Threshold Voltage V GS(TH) V GS =, I D = µa. -. V Zero-Gate Voltage Drain Current I DSS = Rated BS, V GS = V - - µa =.8 x Rated BS, V GS = V, T J = o C - - µa On-State Drain Current (Note ) I D(ON) > I D(ON) x r DS(ON)MAX,V GS = V. - - A Gate to Source Leakage I GSS V GS = ±V - - ± na Drain to Source On Resistance (Note ) r DS(ON) V GS = V, I D =.A (Figures 8, 9) -.. Ω Forward Transconductance (Note ) g fs V, I D =.7A (Figure ).. - S Turn-On Delay Time t d(on) V DD = V, I D.A, R G = Ω, R L = Ω - 7 ns Rise Time t MOSFET Switching Times are Essentially r - ns Independent of Operating Temperature. Turn-Off Delay Time t d(off) - ns Fall Time t f - 6 ns Total Gate Charge (Gate to Source + Gate to Drain) Q g(tot) V GS = V, I D.A, =.8 x Rated BS I g(ref) =.ma (Figure ) Gate Charge is Essentially Independent of Operating Temperature. - nc Gate to Source Charge Q gs -. - nc Gate to Drain Miller Charge Q gd - - nc Input Capacitance C ISS V GS = V, = V, f =.MHz (Figure ) pf Output Capacitance C OSS - - pf Reverse-Transfer Capacitance C RSS - - pf Internal Drain Inductance L D Measured from the Contact Screw on Tab to Center of Die Measured from the Drain Lead, 6mm (.in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D -. - nh -. - nh Internal Source Inductance L S Measured from the G nh Source Lead, 6mm L S (.in) From Header to Source Bonding Pad S Thermal Resistance Junction to Case R θjc o C/W Thermal Resistance Junction to Ambient R θja Free Air Operation o C/W L D -

4 IRF8 Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Source to Drain Current I SD Modified MOSFET - -. A D Pulse Source to Drain Current (Note ) I Symbol Showing the SDM A Integral Reverse P-N Junction Diode G S Source to Drain Diode Voltage (Note ) V SD T J = o C, I SD =.A, V GS = V (Figure ) V Reverse Recovery Time t rr T J = o C, I SD =.A, di SD /dt = A/µs 8 76 ns Reverse Recovered Charge Q RR T J = o C, I SD =.A, di SD /dt = A/µs.96.. µc NOTES:. Pulse test: pulse width µs, duty cycle %.. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure ).. V DD = V, starting T J = o C, L = mh, R G = Ω, peak I AS =.A. Typical Performance Curves Unless Otherwise Specified. POWER DISSIPATION MULTIPLIER T C, CASE TEMPERATURE ( o C) 7 T C, CASE TEMPERATURE ( o C) FIGURE. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, NORMALIZED TRANSIENT THERMAL IMPEDANCE.. P DM..... SINGLE PULSE NOTES: t t DUTY FACTOR: D = t /t PEAK T J = P DM x Z θjc x R θjc + T C t, RECTANGULAR PULSE DURATION (s) FIGURE. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -

5 IRF8 Typical Performance Curves Unless Otherwise Specified (Continued) OPERATION IN THIS REGION IS LIMITED BY r DS(ON) 6 V GS = V V GS =.V T C = o C T J = MAX RATED SINGLE PULSE., DRAIN TO SOURCE VOLTAGE (V) µs µs ms ms ms DC V GS =.V V GS =.V V GS =.V PULSE DURATION = 8µs DUTY CYCLE =.% MAX, DRAIN TO SOURCE VOLTAGE (V) FIGURE. FORWARD BIAS SAFE OPERATING AREA FIGURE. OUTPUT CHARACTERISTICS PULSE DURATION = 8µs DUTY CYCLE =.% MAX V GS = V V GS =.V V GS =.V V GS =.V V GS =.V 6 8, DRAIN TO SOURCE VOLTAGE (V) I DS(ON), DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE =.% MAX > I D(ON) x r DS(ON)MAX T J = o C T J = o C T J = - o C 6 7 V GS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) 8 6 PULSE DURATION = 8µs DUTY CYCLE =.% MAX V GS = V V GS = V NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 8µs DUTY CYCLE =.% MAX I D =.A, V GS = V 8 6 T C, CASE TEMPERATURE ( o C) T J, JUNCTION TEMPERATURE ( o C) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE -

6 IRF8 Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE I D = µa C, CAPACITANCE (pf) 6 8 C ISS C OSS C RSS V GS = V, f = MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GS T J, JUNCTION TEMPERATURE ( o C), DRAIN TO SOURCE VOLTAGE (V) FIGURE. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE g fs, TRANSCONDUCTANCE (S) PULSE DURATION = 8µs DUTY CYCLE =.% MAX T J = - o C T J = o C T J = o C I SD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE =.% MAX T J = o C T J = o C V SD, SOURCE TO DRAIN VOLTAGE (V) FIGURE. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE. SOURCE TO DRAIN DIODE VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) I D =.A = V = V = V 8 6 Q g, GATE CHARGE (nc) FIGURE. GATE TO SOURCE VOLTAGE vs GATE CHARGE -

7 IRF8 Test Circuits and Waveforms BS L t P VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G + V DD - I AS V DD DUT V t P I AS.Ω t AV FIGURE. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 6. UNCLAMPED ENERGY WAVEFORMS t ON t d(on) t OFF t d(off) R L t r t f 9% 9% + R G V DD - % % DUT 9% V GS V GS % % PULSE WIDTH % FIGURE 7. SWITCHING TIME TEST CIRCUIT FIGURE 8. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR (ISOLATED SUPPLY) V DD V BATTERY.µF kω.µf SAME TYPE AS DUT Q gs Q gd Q g(tot) V GS D G DUT I g(ref) I G CURRENT SAMPLING RESISTOR S I D CURRENT SAMPLING RESISTOR I g(ref) FIGURE 9. GATE CHARGE TEST CIRCUIT FIGURE. GATE CHARGE WAVEFORMS -6

8 IRF8 All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 88, Mail Stop - Melbourne, FL 9 TEL: (7) 7-7 FAX: (7) 7-7 For information regarding Intersil Corporation and its products, see web site EUROPE Intersil SA Mercure Center, Rue de la Fusee Brussels, Belgium TEL: ().7. FAX: ().7.. ASIA Intersil (Taiwan) Ltd. 7F-6, No. Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 76 9 FAX: (886) 7 9-7