CDP1881C, CDP1882, CDP1882C

Transcription

1 March 1997 Features P11, P12, P12 MOS 6-Bit Latch and ecoder Memory Interfaces escription Performs Memory Address Latch and ecoder Functions Multiplexed or Non-Multiplexed ecodes Up to 16K Bytes of Memory Interfaces irectly with P100-Series Microprocessors at Maximum lock Frequency an Replace P166 and P167 (Upward Speed and Function apability) Ordering Information PAKAGE 5V 10V TEMP. RANGE ( o ) PKG. NO. PIP P11E to +5 E20.3 PIP P12E to +5 E1.3 PIP Burn-In P12EX to +5 E1.3 SBIP - P12-40 to The P11, P12 and P12 are MOS 6-bit memory latch and decoder circuits intended for use in P100 series microprocessor systems. They can interface directly with the multiplexed address bus of this system at maximum clock frequency, and up to four -bit memories to provide a 16K byte memory system. With four 2K x -bit memories an K byte system can be decoded. The devices are also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to V, the latches are in the data-following mode and the decoded outputs can be used in general purpose memorysystem applications. The P11, P12 and P12 are intended for use with 2K or 4K byte RAMs and are identical except that in the P12 and MR are excluded. The P12 is functionally identical to the P12. It differs in that the P12 has recommended operating voltage range of 4V to 10.5V and the version has a recommended operating voltage range of 4V to 6.5V. The P11, P12 and P12 are supplied in 20 lead and 1 lead packages, respectively. The P11 is supplied only in a dual-in-line plastic package (E suffix). The P12 is supplied in dual-in-line, hermetic side-brazed ceramic ( suffix) and in plastic (E suffix) packages. Pinouts P11 (PIP) TOP VIEW P12, P12 (PIP, ERIP) TOP VIEW LOK 1 20 V LOK 1 1 V MA A MA A MA4 3 1 A9 MA A9 MA A10 MA A10 MA2 MA1 MA0 MR V SS S0 S1 S2 S3 E MA2 MA1 MA0 E V SS S0 S1 S2 S3 AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures. or opyright Intersil orporation File Number

2 P11, P12, P12 Absolute Maximum Ratings Supply Voltage Range, (V ) (All Voltages Referenced to V SS Terminal) P V to +11V P11 and P V to +7V Input Voltage Range, All Inputs V to V +0.5V Input urrent, Any One Input ±10mA Thermal Information Thermal Resistance (Typical) θ JA ( o /W) θ J ( o /W) 1 Lead PIP N/A 20 Lead PIP N/A SBIP Package evice issipation Per Output Transistor T A = Full Package Temperature Range (All Package Types) mW Operating Temperature Range (T A ) Package Type o to +125 o Package Type E o to +5 o Storage Temperature Range (T STG ) o to +150 o Lead Temperature (uring Soldering) At distance 1/16 ±1/32 In. (1.59 ± 0.79mm) from case for 10s max o AUTION: Stresses above those listed in the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Recommended Operating onditions At T A = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: P12 P11, P12 Operating Voltage Range V Input Voltage Range V SS V V SS V V Static Electrical Specifications At T A = -40 o to +5 o, V ± 5%, Except as Noted: ONITIONS P12 P11, P12 SYMBOL V O V IN V uiescent evice urrent Output Low rive (Sink) urrent Output High rive (Source) urrent Output Voltage Low-Level (Note 2) Output Voltage High-Level (Note 2) I - 0, µa - 0, µa I OL 0.4 0, ma 0.5 0, ma I OH 4.6 0, ma 9.5 0, ma V OL - 0, V - 0, V V OH - 0, V - 0, V Input Low Voltage V IL 0.5, V 1, V Input High Voltage V IH 0.5, V 1, V 4-2

3 P11, P12, P12 Static Electrical Specifications At T A = -40 o to +5 o, V ± 5%, Except as Noted: (ontinued) ONITIONS P12 P11, P12 SYMBOL V O V IN V Input Leakage urrent I IN Any Input 0, ±1 - - ±1 µa 0, ± µa Operating urrent (Note 2) I 1 0, 5 0, ma 0, 10 0, ma Input apacitance IN pf Output apacitance OUT pf Minimum ata Retention Voltage V R V = V R V ata Retention urrent I R V = 2.4V µa NOTES: 1. Typical values are for T A = +25 o. 2. I OL = I OH = 1µA. 3. Operating current measured at 200kHz for V = 5V and 400kHz for V = 10V, with outputs open circuits (equivalent to typical P100 system at 3.2MHz, 5V; and 6.4MHz, 10V). MA A MA A MA1 6 1 A9 MA A9 MA A10 MA A10 MA MA MA S0 MA S0 MA5 LOK S1 S2 MA5 LOK S1 S2 MR 12 S3 10 S3 9 V = 20 E V = 1 V SS = 10 V SS = 9 E 11 FIGURE 1. FUNTIONAL IAGRAM FOR THE P11 FIGURE 2. FUNTIONAL IAGRAM FOR THE P12, P12 4-3

4 P11, P12, P12 TRUTH TABLE INPUTS OUTPUTS MR E LK MA4 MA5 S0 S1 S2 S3 1 1 X X X X X X 1 X X X X X X X X 0 0 X X Previous State X X X X X X X Previous State NOTE: 1. P11 Only INPUTS OUTPUTS E LK MA0, MA1, MA2, MA3 A, A9, A10, X X X 0 X Previous State Logic 1 = High, Logic 0 = Low, X = on t are ynamic Electrical Specifications at T A = -40 o to +5 o, V ± 5%, t R, t F = 20ns, V IH = 0.7 V, V IL = 0.3 V, L = 100pF, (See Figure 1) P12 P11, P12 V (NOTE 2) (NOTE 2) Minimum Setup Time t MAL ns Memory Address to LOK ns Minimum Hold Time t LMA ns Memory Address After LOK ns Minimum LOK Pulse Width t LL ns ns 4-4

5 P11, P12, P12 ynamic Electrical Specifications at T A = -40 o to +5 o, V ± 5%, t R, t F = 20ns, V IH = 0.7 V, V IL = 0.3 V, L = 100pF, (See Figure 1) (ontinued) P12 P11, P12 V (NOTE 2) (NOTE 2) PROPAGATION ELAY TIMES hip Enable to hip Select t ES ns ns MR or MRW to hip Select (Note 3) t MS ns ns LOK to hip Select t LS ns ns LOK to Address t LA ns ns Memory Address to hip Select t MAS ns ns Memory Address to Address t MAA ns ns NOTES: 1. Typical values are for T A = 25 o. 2. Maximum limits of minimum characteristics are the values above which all devices function. 3. For P11 type only. E VALI HIP ENABLE t ES t ES S0, S1, S2, S3 (A) HIP ENABLE TO HIP SELET PROPAGATION ELAY MR OR t MS t MS S0, S1, S2, S3 (B) MR OR TO HIP SELET PROPAGATION ELAY (P11 ONLY) MA0 - MA5 t MAL t LMA LOK t LL t LS t MAS t MAS S0, S1, S2, S3 t LA t MAA t MAA () MEMORY ARESS SETUP AN HOL TIME FIGURE 3. TIG WAVEFORMS 4-5

6 P11, P12, P12 Signal escriptions/pin Functions LOK: Latch-Input ontrol - a high at the clock input will allow data to pass through the latch to the output pin. ata is latched on the high to low transition of the clock input. This input is connected to TPA in P100-series systems. MA0 - MA3: Address inputs to the high-byte address latches. MA4 - MA5: High byte address inputs decoded to produce chip selects S0 - S3. MR, : MEMORY REA (MR) and MEMORY WRITE () signal inputs on the P11. A low at either input, when the E pin is low, will enable the decoder chip select outputs (S0 - S3). E: HIP ENABLE input - a low at the E input of P12, P12 will enable the chip select decoder. A low at the E input of P11, coincident with a low at either MR or MRW pin, will enable the chip select decoder. A high on this pin forces S0, S1, S2, and S3 to a high (false) state. : Latched high-byte address outputs. S0 - S3: One of four latched and decoded hip Select outputs. V, V SS : Power and ground pins, respectively. Application Information The P11, P12, P12 can interface directly with the multiplexed address bus of the P100- series microprocessor family at maximum clock frequency. A single P11 or P12 is capable of decoding up to 16K-bytes of memory. The P11 is provided with MR and inputs for controlling bus contention, and is especially useful for interfacing with RAMs that do not have an output enable function (OE). Figure 4 shows the P11 in a minimum system configuration which includes the P133 (1K x ) and two 2K x RAMS. The P11 in this example performs the following functions: 1) Latch and decode high-order address bits for use as chip selects. 2) Gate chip selects with MR and to prevent bus contention with the PU. 3) Latch high-order address bits A to. A system using the P12 is shown in Figure 5. The P12 performs the memory address latch and decoder functions. Note that the RAM has an output enable (OE) pin which eliminates the need for MR and inputs on the latch/decoder. Instead, the MR line is connected directly to the RAM output enable (OE) pin. In Figure 6 the P12 is used to decode a 16K-byte system consisting of four M5332s. ARESS BUS MA0 - MA5 WAIT LR TPA P100 SERIES PU TPA P13 1K x LK P11 LATH/ EOER A - A10 (2) 2K x RAMS E A E B S0 S1 S EO E S2 MR MR MR S3 R/W ATA BUS NOTE: E A = E RAM NUMBER 1 E B = E RAM NUMBER 2 FIGURE 4. IMUM 100-SERIES USING THE P11 4-6

7 P11, P12, P12 P12 LATH/ EOER S3 LK S2 E S1 S0 MA0 - MA5 TO OTHER HIP SELETS LR WAIT ARESS BUS TPA P100 SERIES PU ARESS BUS S2 M5332 A - A10 E M6116A 2K x RAM MR SI/OE OE WE ATA BUS FIGURE 5. P100-SERIES SYSTEM USING THE P12 P12 LATH/ EOER LK E S3 S2 S1 S0 MA0 - MA5 WAIT LR ARESS BUS TPA S2 S2 S2 S2 ARESS BUS P100 SERIES PU M5332 M5332 M5332 M5332 MR SI/OE SI/OE SI/OE SI/OE ATA BUS FIGURE 6. 6K-BYTE SYSTEMS USING THE P12 4-7

8 P11, P12, P12 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERIA Intersil orporation P. O. Box 3, Mail Stop Melbourne, FL TEL: (407) FAX: (407) For information regarding Intersil orporation and its products, see web site EUROPE Intersil SA Mercure enter 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) FAX: (32) ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of hina TEL: (6) FAX: (6)