CD4094. CMOS 8-Stage Shift-and-Store Bus Register. Pinout. Features. Functional Diagram Applications. Description. December 1992

Transcription

1 C494 ecember 1992 CMOS 8-Stage Shift-and-Store Bus Register Features Pinout High Voltage Type (2V Rating) 3-State Parallel Outputs for Connection to Common Bus C494BMS TOP VIEW Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading SOBE 1 16 V Medium Speed Operation - 5MHz at (typ) ATA 2 15 ENABLE Standardized Symmetrical Output Characteristics OCK 3 14 Q5 1% Tested for Quiescent Current at 2V Q Q6 Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 1nA at 18V and +25 o C Q2 Q Q7 Q8 Noise Margin (Over Full Package/Temperature Range) - 1V at V = 5V - 2V at V = - 2.5V at V = Q4 VSS Q S QS 5V, and Parametric Ratings Meets All Requirements of JEEC Tentative Standard No. 13B, Standard Specifications for escription of B Series CMOS evices Functional iagram Applications Serial-to-Parallel ata Conversion Remote Control Holding Register ual-rank Shift, Hold, and Bus Applications ATA 2 OCK 3 8-STAGE SHIFT REGISTER SERIAL S 1 Q S 9 QS escription C494BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. ata is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the SOBE input is high. ata in the storage register appears at the outputs whenever the -ENABLE signal is high. SOBE 1 ENABLE 15 8-BIT STORAGE REGISTER 3-STATE S V = 16 VSS = 8 Two serial outputs are available for cascading a number of C494BMS devices. ata is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q S terminal on the next negative clock edge, provides a means for cascading C494BMS devices when the clock rise time is slow. PARALLEL S Q1 - Q8 (TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY) The C494BMS is supplied in these 16 lead outline packages: Braze Seal IP Frit Seal IP Ceramic Flatpack H4X H1F H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3194

2 Specifications C494BMS Absolute Maximum Ratings C Supply Voltage Range, (V) V to +2V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to V +.5V C Input Current, Any One Input ±1mA Operating Temperature Range to +125 o C Package Types, F, K, H Storage Temperature Range (TSTG) o C to +15 o C Lead Temperature (uring Soldering) o C At istance 1/16 ± 1/32 Inch (1.59mm ±.79mm) from case for 1s Maximum Reliability Information Thermal Resistance θ ja θ jc Ceramic IP and FRIT Package o C/W 2 o C/W Flatpack Package o C/W 2 o C/W Maximum Package Power issipation (P) at +125 o C For TA = to +1 o C (Package Type, F, K) mW For TA = +1 o C to +125 o C (Package Type, F, K).....erate Linearity at 12mW/ o C to 2mW evice issipation per Output Transistor mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE 1. C ELECICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current I V = 2V, VIN = V or GN o C - 1 µa o C - 1 µa V = 18V, VIN = V or GN 3-1 µa Input Leakage Current IIL VIN = V or GN V = o C -1 - na o C -1 - na V = 18V na Input Leakage Current IIH VIN = V or GN V = o C - 1 na o C - 1 na V = 18V 3-1 na Output Voltage VOL15 V =, No Load 1, 2, o C, +125 o C, - 5 mv Output Voltage VOH15 V =, No Load (Note 3) 1, 2, o C, +125 o C, V Output Current (Sink) IOL5 V = 5V, VOUT =.4V o C.53 - ma Output Current (Sink) IOL1 V =, VOUT =.5V o C ma Output Current (Sink) IOL15 V =, VOUT = 1.5V o C ma Output Current (Source) IOH5A V = 5V, VOUT = 4.6V o C ma Output Current (Source) IOH5B V = 5V, VOUT = 2.5V o C ma Output Current (Source) IOH1 V =, VOUT = 9.5V o C ma Output Current (Source) IOH15 V =, VOUT = 13.5V o C ma N Threshold Voltage VNTH V =, ISS = -1µA o C V P Threshold Voltage VPTH VSS = V, I = 1µA o C V Functional F V = 2.8V, VIN = V or GN o C VOH > VOL < V V = 2V, VIN = V or GN o C V/2 V/2 V = 18V, VIN = V or GN 8A +125 o C V = 3V, VIN = V or GN 8B Input Voltage Low VIL V = 5V, VOH > 4.5V, VOL <.5V 1, 2, o C, +125 o C, V (Note 2) Input Voltage High (Note 2) VIH V = 5V, VOH > 4.5V, VOL <.5V 1, 2, o C, +125 o C, V Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage Tri-State Output Leakage NOTES: VIL VIH IOZL IOZH V =, VOH > 13.5V, VOL < 1.5V V =, VOH > 13.5V, VOL < 1.5V VIN = V or GN VOUT = V VIN = V or GN VOUT = V 1. All voltages referenced to device GN, 1% testing being implemented. 2. Go/No Go test with limits applied to inputs. 1, 2, o C, +125 o C, - 4 V 1, 2, o C, +125 o C, 11 - V V = 2V o C µa o C µa V = 18V µa V = 2V o C -.4 µa o C - 12 µa V = 18V µa 3. For accuracy, voltage is measured differentially to V. Limit is.5v max

3 Specifications C494BMS TABLE 2. AC ELECICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONITIONS Clock to Serial Output QS Clock to Serial Output Q S Clock to Parallel Output Strobe to Parallel Output Output Enable to Parallel Output Output Enable to Parallel Output Transition Time Maximum Clock Input Frequency TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TPHZ TPZH TPLZ TPZL TTHL TTLH F (Note 2, 3) (Note 2, 3) NOTES: 1. = 5pF, RL = 2K, Input, TF < 2ns. 2. and +125 o C limits guaranteed, 1% testing being implemented. 3. = 5pF, RL = 1K, Input, TF < 2ns. GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS o C - 6 ns 1, o C, - 81 ns o C - 46 ns 1, o C, ns o C - 84 ns 1, o C, ns o C - 58 ns 1, o C, ns o C - 28 ns 1, o C, ns o C - 2 ns 1, o C, - 27 ns o C - 2 ns 1, o C, - 27 ns o C MHz 1, o C,.93 - MHz TABLE 3. ELECICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current I 1, 2, +25 o C - 5 µa +125 o C - 15 µa V =, VIN = V or GN 1, 2, +25 o C - 1 µa +125 o C - 3 µa V =, VIN = V or GN 1, 2, +25 o C - 1 µa +125 o C - 6 µa Output Voltage VOL V = 5V, No Load 1, o C, +125 o C, - 5 mv Output Voltage VOL V =, No Load 1, o C, +125 o C, Output Voltage VOH V = 5V, No Load 1, o C, +125 o C, Output Voltage VOH V =, No Load 1, o C, +125 o C, - 5 mv V V Output Current (Sink) IOL5 V = 5V, VOUT =.4V 1, o C.36 - ma.64 - ma Output Current (Sink) IOL1 V =, VOUT =.5V 1, o C.9 - ma ma 7-185

4 Specifications C494BMS Output Current (Sink) IOL15 V =, VOUT = 1.5V 1, o C ma ma Output Current (Source) IOH5A V = 5V, VOUT = 4.6V 1, o C ma ma Output Current (Source) IOH5B V = 5V, VOUT = 2.5V 1, o C ma ma Output Current (Source) IOH1 V =, VOUT = 9.5V 1, o C ma ma Output Current (Source) IOH15 V =, VOUT = 13.5V 1, o C ma - - ma Input Voltage Low VIL V =, VOH > 9V, VOL < 1V 1, o C, +125 o C, - 3 V Input Voltage High VIH V =, VOH > 9V, VOL < 1V 1, o C, +125 o C, Clock to Serial Output Qs Clock to Serial Output Q s Clock to Parallel Output Strobe to Parallel Output Output Enable to Parallel Output Output Enable to Parallel Output Transition Time Maximum Clock Input Frequency Minimum ata Setup Time Maximum Clock Input Rise and Fall Time Minimum Clock Pulse Width TABLE 3. ELECICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONITIONS NOTES TEMPERATURE TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TPHZ TPZH TPLZ TPZL TTLH TTHL 7 - V V = 1, 2, o C - 25 ns V = 1, 2, o C - 19 ns V = 1, 2, o C - 22 ns V = 1, 2, o C - 15 ns V = 1, 2, o C - 39 ns V = 1, 2, o C - 27 ns V = 1, 2, o C - 29 ns V = 1, 2, o C - 2 ns V = 1, 2, o C - 12 ns V = 1, 2, o C - 9 ns V = 1, 2, o C - 1 ns V = 1, 2, o C - 8 ns V = 1, 2, o C - 1 ns V = 1, 2, o C - 8 ns F V = 1, 2, o C MHz V = 1, 2, o C 3 - MHz TS V = 5V 1, 2, o C ns V = 1, 2, o C - 55 ns V = 1, 2, o C - 35 ns TF V = 5V 1, 2, 3, o C - 15 µs V = 1, 2, 3, o C - 5 µs V = 1, 2, 3, o C - 5 µs TW V = 5V 1, 2, o C - 2 ns V = 1, 2, o C - 1 ns V = 1, 2, o C - 83 ns MIN MAX UNITS 7-186

5 Specifications C494BMS TABLE 3. ELECICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONITIONS NOTES TEMPERATURE Minimum Strobe Pulse TW V = 5V 1, 2, o C - 2 ns Width V = 1, 2, o C - 8 ns V = 1, 2, o C - 7 ns Input Capacitance CIN Any Input 1, o C pf NOTES: 1. All voltages referenced to device GN. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. = 5pF, RL = 2K, Input, TF < 2ns. 4. = 5pF, RL = 1K, Input, TF < 2ns. 5. If more than one unit is cascaded, should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. MIN MAX UNITS TABLE 4. POST IRRAIATION ELECICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current I V = 2V, VIN = V or GN 1, o C - 25 µa N Threshold Voltage VNTH V =, ISS = -1µA 1, o C V N Threshold Voltage VTN V =, ISS = -1µA 1, o C - ±1 V elta P Threshold Voltage VTP VSS = V, I = 1µA 1, o C V P Threshold Voltage VTP VSS = V, I = 1µA 1, o C - ±1 V elta Functional F V = 18V, VIN = V or GN V = 3V, VIN = V or GN o C VOH > V/2 Time TPHL TPLH NOTES: 1. All voltages referenced to device GN. 2. = 5pF, RL = 2K, Input, TF < 2ns. VOL < V/2 V = 5V 1, 2, 3, o C x +25 o C Limit 3. See Table 2 for +25 o C limit. 4. Read and Record V ns TABLE 5. BURN-IN AN LIFE TEST ELTA PARAMETERS +25 o C PARAMETER SYMBOL ELTA LIMIT Supply Current - MSI-2 I ± 1.µA Output Current (Sink) IOL5 ± 2% x Pre-Test Reading Output Current (Source) IOH5A ± 2% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-ST-883 CONFORMANCE GROUP METHO GROUP A SUBGROUPS REA AN RECOR Initial Test (Pre Burn-In) 1% 54 1, 7, 9 I, IOL5, IOH5A 7-187

6 Specifications C494BMS CONFORMANCE GROUP TABLE 6. APPLICABLE SUBGROUPS MIL-ST-883 METHO GROUP A SUBGROUPS REA AN RECOR Interim Test 1 (Post Burn-In) 1% 54 1, 7, 9 I, IOL5, IOH5A Interim Test 2 (Post Burn-In) 1% 54 1, 7, 9 I, IOL5, IOH5A PA (Note 1) 1% 54 1, 7, 9, eltas Interim Test 3 (Post Burn-In) 1% 54 1, 7, 9 I, IOL5, IOH5A PA (Note 1) 1% 54 1, 7, 9, eltas Final Test 1% 54 2, 3, 8A, 8B, 1, 11 Group A Sample 55 1, 2, 3, 7, 8A, 8B, 9, 1, 11 Group B Subgroup B-5 Sample 55 1, 2, 3, 7, 8A, 8B, 9, 1, 11, eltas Subgroups 1, 2, 3, 9, 1, 11 Subgroup B-6 Sample 55 1, 7, 9 Group Sample 55 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL OSE IRRAIATION MIL-ST-883 TEST REA AN RECOR CONFORMANCE GROUPS METHO PRE-IRRA POST-IRRA PRE-IRRA POST-IRRA Group E Subgroup , 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AN IRRAIATION TEST CONNECTIONS FUNCTION OPEN GROUN V 9V ± -.5V Static Burn-In 1 4-7, , 8, (Note 1) Static Burn-In 2 (Note 1) ynamic Burn- In (Note 1) Irradiation (Note 2) 4-7, , 15, 16 OSCILLATOR 5kHz 25kHz - 8 1, 15, , , , 15, 16 NOTES: 1. Each pin except V and GN will have a series resistor of 1K ± 5%, V = 18V ±.5V 2. Each pin except V and GN will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, failures, V = ±.5V 7-188

7 C494BMS SERIAL IN * 2 1 Q 2 Q Q 8 Q n p SERIAL OUT Q S 1 OCK * 3 SOBE * 1 ENABLE * 15 LATCH 1 p n p n LATCH 2 STAGES 3-7 LATCH 8 p n SERIAL OUT QS 9 * V p 3-STATE 1 n 3 - STATE STATE 8 VSS * ALL INPUTS PROTECTE BY CMOS PROTECTION NETWORK V VSS Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 FIGURE 1. LOGIC IAGRAM UTH TABLE PARALLEL S SERIAL S ENABLE SOBE ATA Q1 QN QS* Q S X X OC OC Q7 NC X X OC OC NC Q7 1 X NC NC Q7 NC 1 1 QN-1 Q7 NC QN-1 Q7 NC NC NC NC Q7 = Level Change Logic 1 = High X = on t Care Logic = Low NC = No Change OC = Open Circuit * At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage and the QS output 7-189

8 C494BMS Typical Performance Characteristics LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V RAIN-TO-SOURCE VOLTAGE (VS) (V) FIGURE 2. TYPICAL LOW (SINK) CURRENT ANSFER CHARACTERISTICS RAIN-TO-SOURCE VOLTAGE (VS) (V) FIGURE 3. MINIMUM LOW (SINK) CURRENT CHARACTERISTICS RAIN-TO-SOURCE VOLTAGE (VS) (V) RAIN-TO-SOURCE VOLTAGE (VS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V HIGH (SOURCE) CURRENT (IOH) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = -5V HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 4. TYPICAL HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION ELAY TIME (tphl, tplh) (ns) PROPAGATION ELAY TIME (tphl, tplh) (ns) LOA CAPACITANCE () (pf) LOA CAPACITANCE () (pf) FIGURE 6. OCK-TO-SERIAL QS PROPAGATION ELAY vs FIGURE 7. OCK-TO-SERIAL Q S PROPAGATION ELAY vs 7-19

9 C494BMS Typical Performance Characteristics (Continued) PROPAGATION ELAY TIME (tphl, tplh) (ns) PROPAGATION ELAY TIME (tphl, tplh) (ns) LOA CAPACITANCE () (pf) FIGURE 8. OCK-TO-PARALLEL PROPAGATION ELAY vs PROPAGATION ELAY TIME (tphl, tplh) (ns) tphl tplh 5V LOA CAPACITANCE () (pf) FIGURE 1. ENABLE-TO-PARALLEL PROPAGATION ELAY vs LOA CAPACITANCE () (pf) FIGURE 9. SOBE-TO-PARALLEL PROPAGATION ELAY vs ANSITION TIME (tthl, ttlh) (ns) LOA CAPACITANCE () (pf) 5V FIGURE 11. TYPICAL ANSITION TIME vs LOA CAPACITANCE MAXIMUM OCK FREQUENCY (f MAX) (MHz) LOA CAPACITANCE () = 5PF SUPPLY VOLTAGE (V) (V) POWER ISSIPATION /PACKAGE (P) (µw) ALTERNATING AN 1 PATTERN ENABLE HIGH SOBE HIGH EVERY 8 OCK PULSES SUPPLY VOLTAGE (V) = 5V = 5pF = 15pF INPUT FREQUENCY (fi) (khz) 1 5 FIGURE 12. TYPICAL MAXIMUM-OCK-FREQUENCY vs SUPPLY VOLTAGE FIGURE 13. YNAMIC POWER ISSIPATION vs INPUT OCK FREQUENCY 7-191

10 C494BMS OCK ATA IN SOBE ENABLE INTERNAL Q STATE Q1 STATE INTERNAL Q7 Q7 3 STATE 3 - STATE SERIAL QS SERIAL Q S FIGURE 14. TIMING IAGRAM IGITALLY CONOLLE EQUIPMENT (REQUIRES CONTINUOUS IGITAL CONOL) IGITALLY CONOLLE EQUIPMENT IGITALLY CONOLLE EQUIPMENT C494BMS Q S C494BMS QS C494BMS SOBE OCK SOBE OCK SOBE OCK CONOL AN SYNC CIRCUIY ATA OCK FROM REMOTE CONOL PANEL FIGURE 15. REMOTE CONOL HOLING REGISTER 7-192

11 C494BMS Chip imensions and Pad Layout imensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1-3 inch). METALLIZATION: Thickness: 11kÅ 14kÅ, AL. PASSIVATION: 1.4kÅ kÅ, Silane BON PAS:.4 inches X.4 inches MIN IE THICKNESS:.198 inches inches 193