DATASHEET CD40105BMS. Features. Description. Applications. Pinout. Functional Diagram. CMOS FIFO Register. FN3353 Rev 0.00 Page 1 of 10.

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1 DATASHEET C05BMS CMOS FIFO Register Features Bits x Words High Voltage Type (0V Rating) Independent Asynchronous Inputs and Outputs 3-State Outputs Expandable in Either Direction Status Indicators on Input and Output Reset Capability Standardized Symmetrical Output Characteristics 00% Tested for Quiescent Current at 0V 5V, 0V and 5V Parametric Ratings Maximum Input Current of A at 8V Over Full Package Temperature Range; 00nA at 8V and +5 o C Noise Margin (Over Full Package/Temperature Range) - V at VDD = 5V - V at VDD = 0V -.5V at VDD = 5V Meets All Requirements of JEDEC Tentative Standard No. 3B, Standard Specifications for Description of B Series CMOS Devices Applications Bit Rate Smoothing CPU/Terminal Buffering Data Communications Peripheral Buffering Line Printer Input Buffers Auto Dialers CRT Buffer Memories Radar Data Acquisition Description FN3353 Rev 0.00 C05BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store -bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flipflop, which stores a marker bit. A signifies that the position s data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the 0 state and sees a in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to 0. The first and last control flip-flops have buffered outputs. Since all empty locations bubble automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA- OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until that data have been transferred to the second location. The flag will remain low when all - word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Continued on next page Pinout 3 - STATE CONTROL DIR SI D VSS C05BMS TOP VIEW VDD SO DOR Q0 Q Q Q3 MR Functional Diagram 3-STATE CONTROL D SHIFT IN SHIFT OUT MASTER RESET VDD = VSS = 8 Q0 Q Q Q3 DATA-OUT READY DATA-IN READY FN3353 Rev 0.00 Page of 0

2 C05BMS Unloading Data - As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT- OUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The C05BMS can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions (see Figures 9 and ). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the control logic marker bits to 0. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The C05BMS is supplied in these -lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HX HF HW Logic Diagram MASTER RESET 9 DATA IN READY SHIFT 5 (DIR) OUT 3 - STATE CONTROL (OUTPUT ENABLE) SHIFT IN 3 POSITIONS DATA READY (DOR) R S Q R Q S Q R Q S Q - 5 R Q S Q R S Q D 5 CL CL LATCHES CL CL LATCHES CL CL LATCHES CL CL 3 LATCHES STATE OUTPUT BUFFERS 3 Q0 Q Q 0 Q3 ALL INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK POS POS POS 3 POS VDD CL p n CL DETAIL OF LATCHES CL p n VSS CL FN3353 Rev 0.00 Page of 0

3 C05BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +0V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +0.5V DC Input Current, Any One Input 0mA Operating Temperature Range to +5 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +50 o C Lead Temperature (During Soldering) o C At Distance / /3 Inch (.59mm 0.9mm) from case for 0s Maximum Reliability Information Thermal Resistance ja jc Ceramic DIP and FRIT Package o C/W 0 o C/W Flatpack Package o C/W 0 o C/W Maximum Package Power Dissipation (PD) at +5 o C For T A = to +00 o C (Package Type D, F, K) mW For T A = +00 o C to +5 o C (Package Type D, F, K) Derate Linearity at mw/ o C to 00mW Device Dissipation per Output Transistor mW For T A = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND +5 o C - 0 A +5 o C A VDD = 8V, VIN = VDD or GND 3-0 A Input Leakage Current IIL VIN = VDD or GND VDD = 0 +5 o C na +5 o C na VDD = 8V na Input Leakage Current IIH VIN = VDD or GND VDD = 0 +5 o C - 00 na +5 o C na VDD = 8V 3-00 na Output Voltage VOL5 VDD = 5V, No Load,, 3 +5 o C, +5 o C, - 50 mv Output Voltage VOH5 VDD = 5V, No Load (Note 3),, 3 +5 o C, +5 o C,.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V +5 o C ma Output Current (Sink) IOL0 VDD = 0V, VOUT = 0.5V +5 o C. - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V +5 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V +5 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V +5 o C ma Output Current (Source) IOH0 VDD = 0V, VOUT = 9.5V +5 o C - -. ma Output Current (Source) IOH5 VDD = 5V, VOUT = 3.5V +5 o C ma N Threshold Voltage VNTH VDD = 0V, ISS = -0 A +5 o C V P Threshold Voltage VPTH VSS = 0V, IDD = 0 A +5 o C 0..8 V Functional (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) F VDD =.8V, VIN = VDD or GND VDD = 0V, VIN = VDD or GND +5 o C +5 o C VOH > VDD/ VDD = 8V, VIN = VDD or GND 8A +5 o C VDD = 3V, VIN = VDD or GND 8B VOL < VDD/ VIL VDD = 5V, VOH >.5V, VOL < 0.5V,, 3 +5 o C, +5 o C, -.5 V VIH VDD = 5V, VOH >.5V, VOL < 0.5V,, 3 +5 o C, +5 o C, V Input Voltage Low (Note ) VIL VDD = 5V, VOH > 3.5V, VOL <.5V,, 3 +5 o C, +5 o C, - V Input Voltage High (Note VIH VDD = 5V, VOH > 3.5V, VOL <.5V,, 3 +5 o C, +5 o C, - V ) Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V VDD = 0V +5 o C A +5 o C - - A VDD = 8V A V FN3353 Rev 0.00 Page 3 of 0

4 C05BMS Tri-State Output Leakage NOTES: IOZH TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE ) VIN = VDD or GND VOUT = VDD. All voltages referenced to device GND, 00% testing being implemented.. Go/No Go test with limits applied to inputs. GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS VDD = 0V +5 o C - 0. A +5 o C - A VDD = 8V 3-0. A 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.. VDD =.8V/3.0V, RL = 00K to VDD VDD = 0V/8V, RL = 0K to VDD TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE ) Shift Out or Reset to Data-Out Ready Shift In to Data-In Ready Ripple through Delay Input to Output 3-State Control to Data Out Transition Time Maximum Shift-In or Shift-Out Rate TPHL TPHL TPLH3 TPZH TTHL TTLH VDD = 5V, VIN = VDD or GND (Note, ) VDD = 5V, VIN = VDD or GND (Note, ) VDD = 5V, VIN = VDD or GND (Note, ) VDD = 5V, VIN = VDD or GND (Note, 3) VDD = 5V, VIN = VDD or GND (Note, ) FCL VDD = 5V (Note, ), VIN = VDD or GND NOTES:. CL = 50pF, RL = 00K, Input TR, TF < 0ns.. and +5 o C limits guaranteed, 00% testing being implemented. 3. CL = 50pF, RL = K, Input TR, TF < 0ns. GROUP A SUBGROUPS TEMPERATURE TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS MIN MAX UNITS 9 +5 o C - 30 ns 0, +5 o C, ns 9 +5 o C - 30 ns 0, +5 o C, - 3 ns 9 +5 o C - s 0, +5 o C, - 5. s 9 +5 o C - 80 ns 0, +5 o C, - 38 ns 9 +5 o C - 00 ns 0, +5 o C, - 0 ns 9 +5 o C.5 - MHz 0, +5 o C,. - MHz PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND,, +5 o C - 5 A +5 o C - 50 A VDD = 0V, VIN = VDD or GND,, +5 o C - 0 A +5 o C A VDD = 5V, VIN = VDD or GND,, +5 o C - 0 A +5 o C - 00 A Output Voltage VOL VDD = 5V, No Load, +5 o C, +5 o C, - 50 mv Output Voltage VOL VDD = 0V, No Load, +5 o C, +5 o C, Output Voltage VOH VDD = 5V, No Load, +5 o C, +5 o C, Output Voltage VOH VDD = 0V, No Load, +5 o C, +5 o C, - 50 mv.95 - V V FN3353 Rev 0.00 Page of 0

5 C05BMS Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V, +5 o C ma 0. - ma Output Current (Sink) IOL0 VDD = 0V, VOUT = 0.5V, +5 o C ma. - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V, +5 o C. - ma. - ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V, +5 o C ma ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V, +5 o C ma ma Output Current (Source) IOH0 VDD = 0V, VOUT = 9.5V, +5 o C ma - -. ma Output Current (Source) IOH5 VDD =5V, VOUT = 3.5V, +5 o C - -. ma - -. ma Input Voltage Low VIL VDD = 0V, VOH > 9V, VOL < V, +5 o C, +5 o C, - 3 V Input Voltage High VIH VDD = 0V, VOH > 9V, VOL < V, +5 o C, +5 o C, Shift or Reset to Data Out Ready Ripple through Delay Input to Output Shift-In to Data-In Ready Shift Out to QN Out 3-State Control to Data Out 3-State Control to Data Out Maximum Shift-In or Shift-Out Rate Maximum Shift-In or Shift-Out Rise Time Maximum Shift-In Fall Time Maximum Shift-Out Fall Time TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE - V TPHL VDD = 0V,, 3 +5 o C - 80 ns VDD = 5V,, 3 +5 o C - 30 ns TPLH3 VDD = 0V,, 3 +5 o C - s VDD = 5V,, 3 +5 o C -. s TPHL VDD = 0V,, 3 +5 o C - 30 ns VDD = 5V,, 3 +5 o C - 90 ns TPHL TPLH TPZH TPZL TTHZ TPLZ VDD = 5V,, 3 +5 o C - 0 ns VDD = 0V,, 3 +5 o C ns VDD = 5V,, 3 +5 o C - 50 ns VDD = 0V,, +5 o C - 0 ns VDD = 5V,, +5 o C - 80 ns VDD = 0V,, 3 +5 o C - 00 ns VDD = 5V,, 3 +5 o C - 80 ns FCL VDD = 0V, +5 o C 3 - MHz VDD = 5V, +5 o C - MHz TR VDD = 5V 3 +5 o C - 5 s VDD = 0V 3 +5 o C - 5 s VDD = 5V 3 +5 o C - 5 s TF VDD = 5V 3 +5 o C - 5 s VDD = 0V 3 +5 o C - 5 s VDD = 5V 3 +5 o C - 5 s TF VDD = 5V 3 +5 o C - 5 s VDD = 0V 3 +5 o C - 5 s VDD = 5V 3 +5 o C - 5 s MIN MAX UNITS FN3353 Rev 0.00 Page 5 of 0

6 C05BMS Minimum Master Reset Pulse Width Data-In Ready Pulse Width Data-Out Ready Pulse Width Minimum Shift Out Pulse Width TWH VDD = 5V,, 3 +5 o C - 00 ns VDD = 0V,, 3 +5 o C - 90 ns VDD = 5V,, 3 +5 o C - 0 ns TWL VDD = 5V,, 3 +5 o C - 50 ns VDD = 0V,, 3 +5 o C - 00 ns VDD = 5V,, 3 +5 o C - 0 ns TWL VDD = 5V,, 3 +5 o C - 0 ns VDD = 0V,, 3 +5 o C - 80 ns VDD = 5V,, 3 +5 o C - 30 ns TWL VDD = 5V,, 3 +5 o C - 80 ns VDD = 0V,, 3 +5 o C - 5 ns VDD = 5V,, 3 +5 o C - 55 ns Minimum Data Setup TSU VDD = 5V,, 3 +5 o C - 0 ns Time VDD = 0V,, 3 +5 o C - 0 ns VDD = 5V,, 3 +5 o C - 0 ns Minimum Data Hold Time TH VDD = 5V,, 3 +5 o C ns VDD = 0V,, 3 +5 o C - 50 ns VDD = 5V,, 3 +5 o C - 0 ns Minimum Shift In Pulse TW VDD = 5V,, 3 +5 o C - 00 ns Width VDD = 0V,, 3 +5 o C - 80 ns VDD = 5V,, 3 +5 o C - 0 ns Input Capacitance CIN Any Input, +5 o C -.5 pf NOTES:. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 00K, Input TR, TF < 0ns.. CL = 50pF, RL = K, Input TR, TF < 0ns. TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND, +5 o C - 5 A N Threshold Voltage VNTH VDD = 0V, ISS = -0 A, +5 o C V N Threshold Voltage Delta VTN VDD = 0V, ISS = -0 A, +5 o C - V P Threshold Voltage VTP VSS = 0V, IDD = 0 A, +5 o C 0..8 V P Threshold Voltage Delta VTP VSS = 0V, IDD = 0 A, +5 o C - V Functional F VDD = 8V, VIN = VDD or GND +5 o C VOH > VOL < V VDD = 3V, VIN = VDD or GND VDD/ VDD/ Time TPHL TPLH VDD = 5V,, 3, +5 o C -.35 x +5 o C Limit ns NOTES: TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE. All voltages referenced to device GND.. CL = 50pF, RL = 00K, Input TR, TF < 0ns. 3. See Table for +5 o C limit.. Read and Record MIN MAX UNITS FN3353 Rev 0.00 Page of 0

7 C05BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 o C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI- IDD.0 A Output Current (Sink) IOL5 0% x Pre-Test Reading Output Current (Source) IOH5A 0% x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 00% 500,, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 00% 500,, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 00% 500,, 9 IDD, IOL5, IOH5A PDA (Note ) 00% 500,, 9, Deltas Interim Test 3 (Post Burn-In) 00% 500,, 9 IDD, IOL5, IOH5A PDA (Note ) 00% 500,, 9, Deltas Final Test 00% 500, 3, 8A, 8B, 0, Group A Sample 5005,, 3,, 8A, 8B, 9, 0, Group B Subgroup B-5 Sample 5005,, 3,, 8A, 8B, 9, 0,, Deltas Subgroups,, 3, 9, 0, Subgroup B- Sample 5005,, 9 Group D Sample 5005,, 3, 8A, 8B, 9 Subgroups, 3 NOTE:. 5% Parameteric, 3% Functional; Cumulative for Static and. TABLE. TOTAL DOSE IRRADIATION MIL-STD-883 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 5005,, 9 Table, 9 Table TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 5kHz Static Burn-In Note, 0 -, 3-9, 5 Static Burn-In Note, 0-8, 3 -, 9, 5, Dynamic Burn-In Note -, 8, 9, 0-3, 5 - Irradiation Note, 0-8, 3 -, 9, 5, NOTES:. Each pin except VDD and GND will have a series resistor of 0K 5%, VDD = 8V 0.5V. Each pin except VDD and GND will have a series resistor of K 5%; Group E, Subgroup, sample size is dice/wafer, 0 failures, VDD = 0V 0.5V FN3353 Rev 0.00 Page of 0

8 C05BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) AMBIENT TEMPERATURE (T A ) = +5 o C GATE-TO-SOURCE VOLTAGE (VGS) = 5V 0V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) AMBIENT TEMPERATURE (T A ) = +5 o C GATE-TO-SOURCE VOLTAGE (VGS) = 5V 0V 5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (T A ) = +5 o C GATE-TO-SOURCE VOLTAGE (VGS) = -5V -0V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (T A ) = +5 o C GATE-TO-SOURCE VOLTAGE (VGS) = -5V -0V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS TRANSITION TIME (tthl, ttlh) (ns) AMBIENT TEMPERATURE (T A ) = +5 o C SUPPLY VOLTAGE (VDD) = 5V 00 0V 5V LOAD CAPACITANCE (CL) (pf) POWER DISSIPATION PER GATE (PD) ( W) (ALL Q OUTPUTS LOADED) AMBIENT TEMPERATURE (T A ) = +5 o C SUPPLY VOLTAGE (VDD) = 5V 5V 0V 0V CL = 50pF CL = 5pF INPUT FREQUENCY (fin) (khz) FIGURE. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY FN3353 Rev 0.00 Page 8 of 0

9 C05BMS INPUT BUFFERS OUTPUT BUFFERS 3 Q0 D 5 DATA-IN READY (DIR) x DATA REGISTER Q 0 Q3 Q 3-STATE CONTROL SI D DOR Q0 Q Q Q3 SI D DOR Q0 Q Q Q3 3 SHIFT IN (SI) CONTROL LOGIC 9 MASTER RESET (MR) DATA-OUT READY (DOR) 5 SHIFT OUT (SO) FIGURE 8. C05BMS FUNCTIONAL BLOCK DIAGRAM FIGURE 9. EXPANSION, -BITS WIDE-BY- N-BITS LONG MASTER RESET INPUTS SHIFT IN (DATA VALID) s SHIFT-IN PULSES HAVE NO EFFECT SHIFT OUT OUTPUTS INPUT READY (CLEAR OUT) OUTPUT READY (CLEAR OUT) SHIFT-OUT PULSES HAVE NO EFFECT s DATA IN (Dn) INPUTS 3-STATE (OUTPUT ENABLE) DATA OUT (UNKNOWN) HIGH Z AT VDD =5V - RIPPLE TIME FROM POSITION TO POSITION AT VDD = 5V - RIPPLE TIME FROM POSITION TO POSITION 0 0 INVALID DATA VALID goes to high level in advance of the DATA OUT by maximum of 50ns at VDD = 5V, 5ns at VDD = 0V, and 0ns at VDD = 5V for CL = 50pF and T A = 5 o C FIGURE 0. TIMING DIAGRAM FOR THE C05BMS FN3353 Rev 0.00 Page 9 of 0

10 C05BMS SHIFT IN DATA OUT READY SI DOR Q0 Q D Q Q3 SI DOR Q0 Q D Q Q3 8 BIT DATA 8 BIT DATA SI DOR Q0 Q D Q Q3 SI DOR Q0 Q D Q Q3 DATA IN READY SHIFT OUT MASTER RESET Pulse must be applied for cascading by N bits. FIGURE. EXPANSION, 8-BITS-WIDE-BY- N-BITS LONG USING C05BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (0-3 inch). METALLIZATION: Thickness: kå kå, AL. PASSIVATION: 0.kÅ - 5.kÅ, Silane BOND PADS: 0.00 inches X 0.00 inches MIN DIE THICKNESS: inches inches Copyright Intersil Americas LLC 999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3353 Rev 0.00 Page 0 of 0