DATASHEET ACTS373MS. Features. Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW.

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1 Radiation Hardened Octal Transparent Latch, Three-State NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at INTERSIL or DATASHEET FN4000 Rev 0.00 Features 1.25 Micron Radiation Hardened SOS CMOS Total Dose 300K RAD (Si) Single Event Upset (SEU) Immunity <1 x Errors/Bit-Day (Typ) SEU LET Threshold >80 MEV-cm 2 /mg Dose Rate Upset >10 11 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55 o C to +125 o C Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min Input Current 1 A at VOL, VOH Description The Intersil ACTS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable (LE) is high. When the LE goes low, the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ACTS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE ACTS373DMSR -55 o C to +125 o C Intersil Class S Equivalent 20 Lead SBDIP ACTS373KMSR -55 o C to +125 o C Intersil Class S Equivalent 20 Lead Ceramic Flatpack ACTS373D/Sample +25 o C Sample 20 Lead SBDIP ACTS373K/Sample +25 o C Sample 20 Lead Ceramic Flatpack ACTS373HMSR +25 o C Die Die Truth Table OE LE D Q Functional Diagram L H H H L H L L L L I L L L h H H X X Z L = Low Voltage Level X = Don t Care H = High Voltage Level Z = High Impedance State I = Low voltage level one set-up time prior to the high to low latch enable transition h = High voltage level one set-up time prior to the high to low latch enable transition 1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) D COMMON CONTROLS LE (11) OE (1) LATCH D Q LE OE Q (2, 5, 6, 9, 12, 15, 16, 19) FN4000 Rev 0.00 Page 1 of 10

2 Absolute Maximum Ratings Supply Voltage V to +6.0V Input Voltage Range, All Inputs V to VCC +0.5V DC Input Current, Any One Input 10mA DC Drain Current, Any One Output 50mA Storage Temperature Range (TSTG) o C to +150 o C Lead Temperature (Soldering 10s) o C Junction Temperature (TJ) o C ESD Classification Class 1 (All Voltages Reference to S) Reliability Information Thermal Impedance JA JC DIP o C/W 24 o C/W Flatpack o C/W 28 o C/W Maximum Package Power Dissipation at +125 o C DIP W Flatpack W Maximum Device Power Dissipation (TBD)W Gate Count Gates CAUTION: As with all semiconductors, stress listed under Absolute Maximum Ratings may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under Electrical Performance Characteristics are the only conditions recommended for satisfactory device operation. Operating Conditions Supply Voltage (VCC) V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) ns/V Max Operating Temperature Range (T A ) o C to +125 o C Input High Voltage (VIH) VCC to VCC/2V Input Low Voltage (VIL) V to 0.8V TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL (NOTE 1) CONDITIONS GROUP A SUB- GROUPS TEMPERATURE MIN LIMITS MAX UNITS Supply Current ICC VCC = 5.5V, VIN = VCC or GND o C - 20 A 2, o C, -55 o C A Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC -0.4V,, (Note 2) o C ma 2, o C, -55 o C -8 - ma Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V,, (Note 2) o C 12 - ma 2, o C, -55 o C 8 - ma Output Voltage High VOH VCC = 5.5V, VIH = 2.75V VIL = 0.8V, IOH = -50 A VIL = 0.8V, IOH = -50 A 1, 2, o C, +125 o C, -55 o C VCC , 2, o C, +125 o C, -55 o C VCC V - V Output Voltage Low VOL VCC = 5.5V, VIH = 2.75V VIL = 0.8V, IOH = 50 A VIL = 0.8V, IOH = 50 A 1, 2, o C, +125 o C, -55 o C V 1, 2, o C, +125 o C, -55 o C V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND o C A 2, o C, -55 o C A Three-State Output Leakage Current IOZ VCC = 5.5V, Force Voltage = 0V or VCC o C - 1 A 2, o C, -55 o C - 35 A Noise Immunity Functional Test FN VIL = 0.8V, (Note 3) 7, 8A, 8B +25 o C, +125 o C, -55 o C - - V 1. All voltages referenced to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests, VO 4.0V is recognized as a logic 1, and VO 0.5V is recognized as a logic 0. FN4000 Rev 0.00 Page 2 of 10

3 PARAMETER SYMBOL TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTES 1, 2) CONDITIONS Propagation Delay TPHL1 TPLH1 TPHL2 TPLH2 TPZL1 TPLZ1 TPHZ1 TPZH1 GROUP A SUB- GROUPS 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns. TEMPERATURE MIN LIMITS MAX UNITS o C 2 19 ns 10, o C, -55 o C 2 21 ns o C 2 18 ns 10, o C, -55 o C 2 20 ns o C 2 17 ns 10, o C, -55 o C 2 18 ns o C 2 17 ns 10, o C, -55 o C 2 19 ns o C 2 18 ns 10, o C, -55 o C 2 20 ns o C 2 18 ns 10, o C, -55 o C 2 18 ns o C 2 19 ns 10, o C, -55 o C 2 20 ns o C 2 17 ns 10, o C, -55 o C 2 18 ns TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTE TEMP MIN TYP MAX UNITS Capacitance Power Dissipation CPD VCC = 5.0V, VIH = 5.0V,, f = 1MHz o C pf +125 o C pf Input Capacitance CIN VCC = 5.0V, VIH = 5.0V,, f = 1MHz Output Capacitance COUT VCC = 5.0V, VIH = 5.0V,, f = 1MHz Pulse Width Time TW VCC = 4.5V, VIH = 4.5V, Setup Time TSU VCC = 4.5V, VIH = 4.5V, Hold Time TH VCC = 4.5V, VIH = 4.5V, o C pf +125 o C pf o C pf +125 o C pf o C ns +125 o C ns o C ns +125 o C ns o C ns +125 o C ns 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. FN4000 Rev 0.00 Page 3 of 10

4 TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL (NOTE 1) CONDITIONS TEMP MIN RAD LIMITS MAX UNITS Supply Current ICC VCC = 5.5V, VIN = VCC or GND +25 o C A Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0 Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 Output Voltage High VOH VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = -50 A VIL = 0.8V, IOH = -50 A Output Voltage Low VOL VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = 50 A VIL = 0.8V, IOH = 50 A +25 o C -8 - ma +25 o C 8 - ma +25 o C VCC V +25 o C VCC V +25 o C V +25 o C V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25 o C - 1 A Three-State Output Leakage Current IOZ VCC = 5.5V, Force Voltage = 0V or VCC +25 o C - 35 A Noise Immunity Functional Test FN VIL = 0.8V, (Note 2) +25 o C - - V Propagation Delay TPHL1 +25 o C 2 21 ns TPLH1 +25 o C 2 20 ns TPHL2 +25 o C 2 18 ns TPLH2 +25 o C 2 19 ns TPZL1 +25 o C 2 20 ns TPLZ1 +25 o C 2 18 ns TPHZ1 +25 o C 2 20 ns TPZH1 +25 o C 2 18 ns 1. All voltages referenced to device GND. 2. For functional tests, VO 4.0V is recognized as a logic 1, and VO 0.5V is recognized as a logic 0. TABLE 5. DELTA PARAMETERS (+25 o C) PARAMETER SYMBOL (NOTE 1) DELTA LIMIT UNITS Supply Current ICC 4.0 A Three-State Leakage Current IOZ 200 na Output Current IOL/IOH 15 % 1. All delta calculations are referenced to 0 hour readings or pre-life readings. FN4000 Rev 0.00 Page 4 of 10

5 TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test 1 (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test 2 (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test 3 (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A (Note 1) Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6 Sample/5005 1, 7, 9 Group D Sample/5005 1, 7, 9 1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS METHOD TEST READ AND RECORD PRE RAD POST RAD PRE RAD POST RAD Group E Subgroup , 7, 9 Table 4 1, 9 Table 4 (Note 1) 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. BURN-IN TEST CONNECTIONS (+125 o C < TA < 139 o C) OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V STATIC BURN-IN 1 (Note 1) 50kHz 25kHz - 1, 3, 4, 7, 8, 10, 11, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, STATIC BURN-IN 2 (Note 1) , 5, 6, 9, 12, 15, 16, 19 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, DYNAMIC BURN-IN (Note 1) - 1, 10 2, 5, 6, 9, 12, 15, 16, , 4, 7, 8, 13, 14, 17, Each pin except VCC and GND will have a series resistor of 500 5%. TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25 o C, 5 o C) FUNCTION OPEN GROUND VCC = 5V 0.5V Irradiation Circuit (Note 1) 2, 5, 6, 9, 12, 15, 16, , 3, 4, 7, 8, 11, 13, 14, 17, 18, Each pin except VCC and GND will have a series resistor of 47k 5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures. FN4000 Rev 0.00 Page 5 of 10

6 Intersil - Space Products MS Screening Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull Method % Internal Visual Inspection Method % Temperature Cycling Method 1010 Condition C (-65 o to +150 o C) 100% Constant Acceleration 100% PIND Testing 100% External Visual Inspection 100% Serialization 100% Initial Electrical Test 100% Static Burn-In 1 Method 1015, 24 Hours at +125 o C Min 100% Interim Electrical Test 1 (Note 1) 100% Static Burn-In 2 Method 1015, 24 Hours at +125 o C Min 100% Interim Electrical Test 2 (Note 1) 100% Dynamic Burn-In Method 1015, 240 Hours at +125 o C or 180 Hours at +135 o C 100% Interim Electrical Test 3 (Note 1) 100% Final Electrical Test 100% Fine and Gross Seal Method % Radiographics Method 2012 (2 Views) 100% External Visual Method 2009 Group A (All Tests) Method 5005 (Class S) Group B (Optional) Method 5005 (Class S) (Note 2) Group D (Optional) Method 5005 (Class S) (Note 2) CSI and/or GSI (Optional) (Note 2) Data Package Generation (Note 3) 1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity). Certificate of Conformance (as found on shipper). Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number). Variables Data (All Read, Record, and delta operations). Group A Attributes Data Summary. Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. SEM photos to include percent of step coverage. X-Ray Report and Film, including penetrometer measurements. GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose, Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil. Propagation Delay Timing Diagram and Load Circuit VIH INPUT DUT CL 50pF TEST POINT RL 500 S VOH TPLH TPHL VOL OUTPUT AC VOLTAGE LEVELS PARAMETER ACTS UNITS VCC 4.50 V VIH 3.00 V 1.30 V VIL 0 V GND 0 V FN4000 Rev 0.00 Page 6 of 10

7 Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit INPUT VIH TW DUT CL 50pF TEST POINT RL 500 VIL TSU TH INPUT CP VIH TW PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS VIL TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH PARAMETER ACTS UNITS VCC 4.50 V VIH 3.00 V 1.30 V VIL 0 V GND 0 V Three-State High Timing Diagram and Load Circuit VIH S VOH TPZH INPUT TPHZ DUT CL 50pF TEST POINT RL 500 VT OUTPUT VW VOZ PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACTS UNITS VCC 4.50 V VIH 3.00 V 1.30 V VT 1.30 V VW 3.60 V GND 0 V Three-State Low Timing Diagram and Load Circuit VIH VCC S VOZ TPZL INPUT VT TPLZ OUTPUT VW DUT RL 500 CL 50pF TEST POINT VOL PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACTS UNITS VCC 4.50 V VIH 3.00 V 1.30 V VT 1.30 V VW 0.90 V GND 0 V FN4000 Rev 0.00 Page 7 of 10

8 Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSiCu Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max) Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max) GLASSIVATION: Type: SiO 2 Thickness: 8kÅ 1kÅ DIE ATTACH: Material: Silver Glass or JM 7000 after 7/1/95 WORST CASE CURRENT DENSITY: < 2.0 x 10 5 A/cm 2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110 m x 110 m Metallization Mask Layout ACTS373MS D0 (3) Q0 (2) OE (1) VCC (20) Q7 (19) D7 (18) D1 (4) (17) D6 Q1 (5) (16) Q6 NC NC NC NC Q2 (6) (15) Q5 D2 (7) (14) D5 (8) D3 (9) Q3 (10) GND (11) CP (12) Q4 (13) D4 FN4000 Rev 0.00 Page 8 of 10

9 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B S C A - B D A A e D S S D S 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: INCH. E ea -Baaa M c1 L ea/2 LEAD FINISH BASE METAL b1 M (b) SECTION A-A -D- -A- S2 Q -C- A c M C A - B S D S (c) D20.3 MIL-STD-1835 CDIP2-T20 (D-8, CONFIGURATION C) 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e BSC 2.54 BSC - ea BSC 7.62 BSC - ea/ BSC 3.81 BSC - L Q S S o 105 o 90 o 105 o - aaa bbb ccc M N Rev. 0 4/94 FN4000 Rev 0.00 Page 9 of 10

10 Ceramic Metal Seal Flatpack Packages (Flatpack) -Hb A e -A M H A - B Q SEATING AND BASE PLANE L M c1 S E3 D S PIN NO. 1 ID AREA E1 E E2 LEAD FINISH BASE METAL b1 M (b) SECTION A-A M H A - B E3 (c) L S1 C S A A D S -D- -C- -B- D K20.A MIL-STD-1835 CDFP4-F20 (F-9A, CONFIGURATION B) 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b c c D E E E E e BSC 1.27 BSC - k L Q S M N Rev. 0 5/18/94 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: INCH. Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN4000 Rev 0.00 Page 10 of 10