CD4063BMS. CMOS 4-Bit Magnitude Comparator. Pinout. Features. Functional Diagram. Applications. Description. December 1992

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1 CD3BMS December 99 Features CMOS -Bit Magnitude Comparator Pinout High Voltage Type (V Rating) Expansion to 8,,... N Bits by Cascading Units CD3BMS TOP VIEW Medium Speed Operation - Compares Two -Bit Words in 5ns (Typ.) at V VDD % Tested for Quiescent Current at V Standardized Symmetrical Output Characteristics 5V, V and 5V Parametric Ratings Maximum Input Current of µa at 8V Over Full Package Temperature Range; na at 8V and +5 o C Noise Margin (Full Package Temperature Range) - V at VDD = 5V - V at VDD = V -.5V at VDD = 5V (A < B) IN (A = B) IN (A > B) IN (A > B) OUT (A = B) OUT (A < B) OUT VSS A B A B Meets All Requirements of JEDEC Tentative Standard No. 3B, Standard Specifications for Description of B Series CMOS Devices Functional Diagram Applications WORD A Servo Motor Controls Process Controllers A > B A > B Description CD3BMS is a -bit magnitude comparator designed for use in computer and logic applications that require the comparison of two -bit words. This logic circuit determines whether one -bit word (Binary or BCD) is less than, equal to, or greater than a second -bit word. CASCADING INPUTS A = B A < B WORD B A = B A < B The CD3BMS has eight comparing inputs (,, through A, B), three outputs (A < B, A = B, A > B) and three cascading inputs (A < B, A = B, A > B) that permit systems designers to expand the comparator function to 8,,... N bits. When a single CD3BMS is used, the cascading inputs are connected as follows: (A < B) = low, (A = B) = high, (A > B) = low. For words longer than bits, CD3BMS devices may be cascaded by connecting the outputs of the less significant comparator to the corresponding cascading inputs of the more significant comparator. Cascading inputs (A < B, A = B, and A > B) on the least significant comparator are connected to a low, a high, and a low level, respectively. The CD3BMS is supplied in these lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HT HE HW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Corporation File Number 338

2 Specifications CD3BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +.5V DC Input Current, Any One Input ±mA Operating Temperature Range to +5 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +5 o C Lead Temperature (During Soldering) o C At Distance / ± /3 Inch (.59mm ±.79mm) from case for s Maximum Reliability Information Thermal Resistance θ ja θ jc Ceramic DIP Package o C/W C/W Flatpack Package o C/W o C/W Maximum Package Power Dissipation (PD) at +5 o C For TA = to + o C (Package Type D, F, K) mW For TA = + o C to +5 o C (Package Type D, F, K).....Derate Linearity at mw/ o C to mw Device Dissipation per Output Transistor mw For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MA UNITS Supply Current IDD VDD = V, VIN = VDD or GND +5 o C - µa +5 o C - µa VDD = 8V, VIN = VDD or GND 3 - µa Input Leakage Current IIL VIN = VDD or GND VDD = +5 o C - - na +5 o C - - na VDD = 8V na Input Leakage Current IIH VIN = VDD or GND VDD = +5 o C - na +5 o C - na VDD = 8V 3 - na Output Voltage VOL5 VDD = 5V, No Load,, 3 +5 o C, +5 o C, - 5 mv Output Voltage VOH5 VDD = 5V, No Load (Note 3),, 3 +5 o C, +5 o C,.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT =.V +5 o C.53 - ma Output Current (Sink) IOL VDD = V, VOUT =.5V +5 o C. - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V +5 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V +5 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V +5 o C ma Output Current (Source) IOH VDD = V, VOUT = 9.5V +5 o C - -. ma Output Current (Source) IOH5 VDD = 5V, VOUT = 3.5V +5 o C ma N Threshold Voltage VNTH VDD = V, ISS = -µa +5 o C V P Threshold Voltage VPTH VSS = V, IDD = µa +5 o C.7.8 V Functional F VDD =.8V, VIN = VDD or GND 7 +5 o C VOH > VOL < V VDD = V, VIN = VDD or GND 7 +5 o C VDD/ VDD/ VDD = 8V, VIN = VDD or GND 8A +5 o C VDD = 3V, VIN = VDD or GND 8B Input Voltage Low (Note ) VIL VDD = 5V, VOH >.5V, VOL <.5V,, 3 +5 o C, +5 o C, -.5 V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) VIH VDD = 5V, VOH >.5V, VOL <.5V,, 3 +5 o C, +5 o C, V VIL VIH VDD = 5V, VOH > 3.5V, VOL <.5V VDD = 5V, VOH > 3.5V, VOL <.5V NOTES:. All voltages referenced to device GND. % testing being implemented. Go/No Go test with limit applied to inputs,, 3 +5 o C, +5 o C, - V,, 3 +5 o C, +5 o C, - V 3. For accuracy, voltage is measured differentially to VDD. Limit is.5v max

3 Specifications CD3BMS TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL (NOTE, ) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MA UNITS Propagation Delay Comparator Input to Output Propagation Delay Cascade Input to Output TPHL TPLH TPHL TPLH VDD = 5V, VIN = VDD or GND 9 +5 o C - 5 ns, +5 o C, - 88 ns VDD = 5V, VIN = VDD or GND 9 +5 o C - ns, +5 o C, - 35 ns Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +5 o C - ns NOTES:. VDD = 5V, CL = 5pF, RL = K; input TR, TF < ns.. and +5 o C limits guaranteed, % testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, +5 o C, - 7 ns PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MA UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND,, +5 o C - 5 µa +5 o C - 5 µa VDD = V, VIN = VDD or GND,, +5 o C - µa +5 o C - 3 µa VDD = 5V, VIN = VDD or GND,, +5 o C - µa +5 o C - µa Output Voltage VOL VDD = 5V, No Load, +5 o C, +5 o C, - 5 mv Output Voltage VOL VDD = V, No Load, +5 o C, +5 o C, Output Voltage VOH VDD = 5V, No Load, +5 o C, +5 o C, Output Voltage VOH VDD = V, No Load, +5 o C, +5 o C, - 5 mv.95 - V V Output Current (Sink) IOL5 VDD = 5V, VOUT =.V, +5 o C.3 - ma. - ma Output Current (Sink) IOL VDD = V, VOUT =.5V, +5 o C.9 - ma. - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V, +5 o C. - ma. - ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V, +5 o C ma - -. ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V, +5 o C ma - -. ma Output Current (Source) IOH VDD = V, VOUT = 9.5V, +5 o C ma - -. ma Output Current (Source) IOH5 VDD =5V, VOUT = 3.5V, +5 o C - -. ma - -. ma Input Voltage Low VIL VDD = V, VOH > 9V, VOL < V, +5 o C, +5 o C, - 3 V 7-9

4 Specifications CD3BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE Input Voltage High VIH VDD = V, VOH > 9V, VOL < V Propagation Delay Comparator Input to Output Propagation Delay Cascade Input to Output TPHL TPLH TPHL TPLH, +5 o C, +5 o C, +7 - V VDD = V,, 3 +5 o C - 5 ns VDD = 5V,, 3 +5 o C - 35 ns VDD = V,, 3 +5 o C - ns VDD = 5V,, 3 +5 o C - 8 ns Transition Time TTHL VDD = V,, 3 +5 o C - ns TTLH VDD = 5V,, 3 +5 o C - 8 ns Input Capacitance CIN, +5 o C pf NOTES:. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 5pF, RL = K; input TR, TF < ns TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN Supply Current IDD VDD = V, VIN = VDD or GND, +5 o C - 5 µa N Threshold Voltage VNTH VDD = V, ISS = -µa, +5 o C V N Threshold Voltage Delta VNTH VDD = V, ISS= -µa, +5 o C - ± V P Threshold Voltage VPTH VSS = V, IDD = µa, +5 o C..8 V P Threshold Voltage Delta VPTH VSS = V, IDD = µa, +5 o C - ± V Functional F VDD = 8V, VIN = VDD or GND +5 o C VOH > VDD = 3V, VIN = VDD or GND VDD/ Propagation Delay Time TPHL TPLH NOTES:. All voltages referenced to device GND.. VDD = 5V, CL = 5pF, RL = K; input TR, TF = ns 3. See Table for +5 o C limit.. Read and record MA VOL < VDD/ VDD = 5V (Worst Case),, 3, +5 o C -.35 x +5 o C Limit TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI- IDD ±.µa Output Current (Sink) IOL5 ± % x Pre-Test Reading Output Current (Source) IOH5A ± % x Pre-Test Reading MIN MA UNITS UNITS V ns TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) % 5, 7, 9 IDD, IOL5, IOH5A 7-9

5 Specifications CD3BMS TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD Interim Test (Post Burn-In) % 5, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) % 5, 7, 9 IDD, IOL5, IOH5A PDA (Note ) % 5, 7, 9, Deltas Interim Test 3 (Post Burn-In) % 5, 7, 9 IDD, IOL5, IOH5A PDA (Note ) % 5, 7, 9, Deltas Final Test % 5, 3, 8A, 8B,, Group A Sample 55,, 3, 7, 8A, 8B, 9,, Group B Subgroup B-5 Sample 55,, 3, 7, 8A, 8B, 9,,, Deltas Subgroups,, 3, 9,, Subgroup B- Sample 55, 7, 9 Group D Sample 55,, 3, 8A, 8B, 9 Subgroups, 3 NOTE: 5% parametric, 3% functional; cumulative for static and. TABLE 7. TOTAL DOSE IRRADIATION TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 55, 7, 9 Table, 9, Deltas Table TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -.5V 5kHz 5kHz Static Burn-In Note Static Burn-In Note 5-7,,, 8-5 3, 5-7 3, 8,,, 9- Dynamic Burn- In Note -,,, 8,,, 3 3, 5-7, 5 9, Irradiation Note 5-7 3, 8,,, 9- NOTE:. Each pin except VDD and GND will have a series resistor of K ± 5%, VDD = 8V ±.5V. Each pin except VDD and GND will have a series resistor of 7K ± 5%; Group E, Subgroup, sample size is dice/wafer, failures, VDD = V ±.5V A A A A5 A A7 A8 A9 A A VDD CD3 (A < B) IN (A = B) IN (A > B) IN (A < B) OUT (A = B) OUT (A > B) OUT CD3 CD3 B B B B5 B B7 B8 B9 B B tp TOTAL = tp (COMPARE INPUTS) + x tp (CASCADE INPUTS), AT VDD = V (3 STAGES) = 5 + ( x ) = 5ns (TYP.) FIGURE. TYPICAL SPEED CHARACTERISTICS OF A -BIT COMPARATOR 7-9

6 CD3BMS Logic Diagram COMPARING INPUTS A * A * 3 * 5 * B 9 * B * * A A A A B B B B A B A B A B A B (A < B) i - I A < B 7 (A < B) OUT CASCADING INPUTS (A < B) IN (A > B) IN (A = B) IN * * * 3 * (A < B) i - I (A > B) i - I A > B 5 (A = B) OUT (A > B) OUT * ALL INPUTS PROTECTED BY THE CMOS PROTECTION NETWORK INPUT TERMINAL VDD VSS B A B A B A B A (A > B) i - I FIGURE. LOGIC DIAGRAM TRUTH TABLE INPUTS COMPARING CASCADING OUTPUTS,, A, B A, B A <B A = B A > B A < B A = B A > B > < > = = = = = = = < A > B A = B A = B A = B A = B A = B A < B = Don t Care Logic = High Level Logic = Low Level A > B A = B A = B A = B A < B 7-93

7 CD3BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V V 5V 5 5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tthl, ttlh) (ns) 7 SUPPLY VOLTAGE (VDD) = 5V 5 3 V 5V LOAD CAPACITANCE (CL) (pf) PROPAGATION DELAY TIME (tthl, ttlh) (ns) LOAD CAPACITANCE (CL) = 5pF SUPPLY VOLTAGE (VDD) (V) FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE ( COMPARING INPUTS TO OUTPUTS) FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs SUPPLY VOLTAGE ( COMPARING INPUTS TO OUTPUTS) 7-9

8 CD3BMS Typical Performance Characteristics (Continued) TRANSITION TIME (tthl, ttlh) (ns) SUPPLY VOLTAGE (VDD) = 5V 5 V 5V 5 8 LOAD CAPACITANCE (CL) (pf) FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE POWER DISSIPATION PER GATE (PD) (µw) 3 SUPPLY VOLTAGE (VDD) = 5V LOAD CAPACITANCE (CL) = 5pF 5V, 5pF V, 5pF V, 5pF INPUT FREQUENCY (f) (khz) FIGURE. TYPICAL POWER DISSIPATION vs FREQUENCY Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch). METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ - 5.kÅ, Silane BOND PADS:. inches. inches MIN DIE THICKNESS:.98 inches -.8 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site 95

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