DATASHEET CD4028BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS BCD-To-Decimal Decoder. FN3303 Rev 0.
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1 DATASHEET CMOS BCD-To-Decimal Decoder FN Rev. December Features Pinout High Voltage Type (V Rating) BCD-to-Decimal Decoding or Binary-to-Octal Decoding TOP VIEW High Decoded Output Drive Capability Positive Logic Inputs and Outputs - Decoded Outputs Go High On Selection Medium-Speed Operation - tphl, tplh = ns (typ) at VDD = V VDD B C Standardized Symmetrical Output Characteristics D % Tested For Quiescent Current at V A Maximum Input Current of A at V Over Full Package-Temperature Range; - na at V and + o C VSS Noise Margin (Over Full Package Temperature Range): - V at VDD = V - V at VDD = V -.V at VDD = V V, V and V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. B, Standard Specifications for Description of B Series CMOS Devices Applications Code Conversion Indication-Tube Decoder Functional Diagram -BIT BINARY BCD A B C D V DD BUFFERED OCTAL DECODED OUTPUTS ( OF ) BUFFERED DECIMAL DECODED OUTPUTS ( OF ) Address Decoding - Memory Selection Control V SS Description types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all inputs, decoding logic gates, and output buffers. A BCD code applied to the four inputs, A to D, results in a high level at the selected one of decimal decoded outputs. Similarly, a -bit binary code applied to inputs A through C is decoded in octal code at output to if D =. High drive capability is provided at all outputs to enhance dc and dynamic performance in high fan-out applications. The is supplied in these -lead outline packages: Braze Seal DIP HS Frit Seal DIP HE Ceramic Flatpack HX FN Rev. Page of December
2 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +.V DC Input Current, Any One Input ma Operating Temperature Range o C to + o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to + o C Lead Temperature (During Soldering) o C At Distance / / Inch (.mm.mm) from case for s Maximum Reliability Information Thermal Resistance ja jc Ceramic DIP and FRIT Package..... o C/W o C/W Flatpack Package o C/W o C/W Maximum Package Power Dissipation (PD) at + o C For TA = - o C to + o C (Package Type D, F, K) mw For TA = + o C to + o C (Package Type D, F, K)..... Derate Linearity at mw/ o C to mw Device Dissipation per Output Transistor mw For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = V, VIN = VDD or GND + o C - A + o C - A VDD = V, VIN = VDD or GND - o C - A Input Leakage Current IIL VIN = VDD or GND VDD = + o C - - na + o C - - na VDD = V - o C - - na Input Leakage Current IIH VIN = VDD or GND VDD = + o C - na + o C - na VDD = V - o C - na Output Voltage VOL VDD = V, No Load,, + o C, + o C, - o C - mv Output Voltage VOH VDD = V, No Load (Note ),, + o C, + o C, - o C. - V Output Current (Sink) IOL VDD = V, VOUT =.V + o C. - ma Output Current (Sink) IOL VDD = V, VOUT =.V + o C. - ma Output Current (Sink) IOL VDD = V, VOUT =.V + o C. - ma Output Current (Source) IOHA VDD = V, VOUT =.V + o C - -. ma Output Current (Source) IOHB VDD = V, VOUT =.V + o C - -. ma Output Current (Source) IOH VDD = V, VOUT =.V + o C - -. ma Output Current (Source) IOH VDD = V, VOUT =.V + o C - -. ma N Threshold Voltage VNTH VDD = V, ISS = - A + o C V P Threshold Voltage VPTH VSS = V, IDD = A + o C.. V Functional F VDD =.V, VIN = VDD or GND + o C VOH > VOL < V VDD = V, VIN = VDD or GND + o C VDD/ VDD/ VDD = V, VIN = VDD or GND A + o C VDD = V, VIN = VDD or GND B - o C Input Voltage Low (Note ) VIL VDD = V, VOH >.V, VOL <.V,, + o C, + o C, - o C -. V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VIH VDD = V, VOH >.V, VOL <.V,, + o C, + o C, - o C. - V VIL VIH VDD = V, VOH >.V, VOL <.V VDD = V, VOH >.V, VOL <.V. All voltages referenced to device GND, % testing being implemented.. Go/No Go test with limits applied to inputs.,, + o C, + o C, - o C - V,, + o C, + o C, - o C - V. For accuracy, voltage is measured differentially to VDD. Limit is.v max. FN Rev. Page of December
3 TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS (NOTE, ) SUBGROUPS TEMPERATURE MIN MAX UNITS Propagation Delay TPHL VDD = V, VIN = VDD or GND + o C - ns TPLH, + o C, - o C - ns Transition Time TTHL VDD = V, VIN = VDD or GND + o C - ns TTLH, + o C, - o C - ns NOTES:. CL = pf, RL = K, Input TR, TF < ns.. - o C and + o C limits guaranteed, % testing being implemented. TABLE. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = V, VIN = VDD or GND, - o C, + o C - A + o C - A VDD = V, VIN = VDD or GND, - o C, + o C - A + o C - A VDD = V, VIN = VDD or GND, - o C, + o C - A + o C - A Output Voltage VOL VDD = V, No Load, + o C, + o C, - mv - o C Output Voltage VOL VDD = V, No Load, + o C, + o C, - o C Output Voltage VOH VDD = V, No Load, + o C, + o C, - o C Output Voltage VOH VDD = V, No Load, + o C, + o C, - o C - mv. - V. - V Output Current (Sink) IOL VDD = V, VOUT =.V, + o C. - ma - o C. - ma Output Current (Sink) IOL VDD = V, VOUT =.V, + o C. - ma - o C. - ma Output Current (Sink) IOL VDD = V, VOUT =.V, + o C. - ma - o C. - ma Output Current (Source) IOHA VDD = V, VOUT =.V, + o C - -. ma - o C - -. ma Output Current (Source) IOHB VDD = V, VOUT =.V, + o C - -. ma - o C - -. ma Output Current (Source) IOH VDD = V, VOUT =.V, + o C - -. ma - o C - -. ma Output Current (Source) IOH VDD =V, VOUT =.V, + o C - -. ma - o C - -. ma Input Voltage Low VIL VDD = V, VOH > V, VOL < V, + o C, + o C, - o C - V Input Voltage High VIH VDD = V, VOH > V, VOL < V, + o C, + o C, - o C - V FN Rev. Page of December
4 Propagation Delay TABLE. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE TPHL TPLH VDD = V,, + o C - ns VDD = V,, + o C - ns Transition Time TTHL VDD = V,, + o C - ns TTLH VDD = V,, + o C - ns Input Capacitance CIN, + o C -. pf NOTES:. All voltages referenced to device GND.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. CL = pf, RL = K, Input TR, TF < ns. MIN LIMITS MAX UNITS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = V, VIN = VDD or GND, + o C - A N Threshold Voltage VNTH VDD = V, ISS = - A, + o C V N Threshold Voltage VTN VDD = V, ISS = - A, + o C - V Delta P Threshold Voltage VTP VSS = V, IDD = A, + o C.. V P Threshold Voltage VTP VSS = V, IDD = A, + o C - V Delta Functional F VDD = V, VIN = VDD or GND VDD = V, VIN = VDD or GND + o C VOH > VDD/ Propagation Delay Time TPHL TPLH NOTES:. All voltages referenced to device GND.. CL = pf, RL = K, Input TR, TF < ns. VOL < VDD/ VDD = V,,, + o C -. x + o C Limit. See Table for + o C limit.. Read and Record V ns TABLE. BURN-IN AND LIFE TEST DELTA PARAMETERS + O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI- IDD. A Output Current (Sink) IOL % x Pre-Test Reading Output Current (Source) IOHA % x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) %,, IDD, IOL, IOHA Interim Test (Post Burn-In) %,, IDD, IOL, IOHA Interim Test (Post Burn-In) %,, IDD, IOL, IOHA PDA (Note ) %,,, Deltas Interim Test (Post Burn-In) %,, IDD, IOL, IOHA PDA (Note ) %,,, Deltas FN Rev. Page of December
5 CONFORMANCE GROUP TABLE. APPLICABLE SUBGROUPS (Continued) MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Final Test %,, A, B,, Group A Sample,,,, A, B,,, Group B Subgroup B- Sample,,,, A, B,,,, Deltas Subgroups,,,,, Subgroup B- Sample,, Group D Sample,,, A, B, Subgroups, NOTE:. % Parameteric, % Functional; Cumulative for Static and. TABLE. TOTAL DOSE IRRADIATION MIL-STD- TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup,, Table, Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD V -.V Static Burn-In -,,,, - Note Static Burn-In Note Dynamic Burn- In Note Irradiation Note -,,, -, OSCILLATOR khz khz - -,,,,, -,,, -, NOTE:. Each pin except VDD and GND will have a series resistor of K %, VDD = V.V. Each pin except VDD and GND will have a series resistor of K %; Group E, Subgroup, sample size is dice/wafer, failures, VDD = V.V FN Rev. Page of December
6 Logic Diagram A B C D VDD ALL ARE PROTECTED BY CMOS PROTECTION NETWORK VSS TABLE. TRUTH TABLE D C B A = HIGH LEVEL = LOW LEVEL FN Rev. Page of December
7 Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = V V V OUTPUT LOW (SINK) CURRENT (IOL) (ma) AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = V V V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT CAPACITANCE DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. MINIMUM OUTPUT LOW (SINK) CURRENT CAPACITANCE PROPAGATION DELAY TIME (tphl, tplh) (ns) AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE (VDD) = V V V LOAD CAPACITANCE (CL) (pf) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = -V -V -V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (T A ) = + o C -V - -V FIGURE. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS - GATE-TO-SOURCE VOLTAGE (VGS) = -V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS POWER DISSIPATION (PD) ( W) AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE (VDD) = V V FIGURE. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY V INPUT FREQUENCY (fi) (khz) V CL = pf CL = pf FN Rev. Page of December
8 Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (T A ) = + o C TRANSITION TIME (tthl, ttlh) (ns) SUPPLY VOLTAGE (VDD) = V V V LOAD CAPACITANCE (CL) (pf) FIGURE. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE Typical Applications The circuit shown in Figure converts any -bit code to a decimal or hexadecimal code. Table shows a number of codes and the decimal or hexadecimal number in these codes which must be applied to the input terminals of the to select a particular output. For example: in order to get a high on output number the input must be either an expressed in -bit Binary code, a expressed in -Bit Gray code, or a expressed in Excess- code. / CDB OUTPUTS FIGURE. CODE CONVERSION CIRCUIT TABLE. CODE CONVERSION CHART HEXA- DECIMAL INPUT CODES DECIMAL OUTPUT NUMBER -BIT BINARY -BIT GRAY EXCESS- EXCESS- GRAY AIKEN --- D C B A FN Rev. Page of December
9 TABLE. CODE CONVERSION CHART (Continued) HEXA- DECIMAL INPUT CODES DECIMAL OUTPUT NUMBER D C B A -BIT BINARY -BIT GRAY EXCESS- EXCESS- GRAY AIKEN --- BCD D C B A (TRADEMARK) BURROUGHS CORP. OF NUMERALS VT TUBE REQUIREMENTS TYPE VT(Vdc) NUMERAL ma/ BURROUGHS B B/ B B TRANSISTOR CHARACTERISTICS Leakage with transistor cutoff.ma V(BR)CEO V FIGURE. NEON READOUT (NIXIE TUBE) DISPLAY APPLICATION E F INHIBIT (NO SELECTION) / CDB OUTPUTS (SELECTED OUTPUT IS HIGH) FIGURE. -BIT BINARY TO -OF- ADDRESS DECODER FN Rev. Page of December
10 Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( - inch) METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BOND PADS:. inches X. inches MIN DIE THICKNESS:. inches -. inches Copyright Intersil Americas LLC. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN Rev. Page of December
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