DATASHEET CD4503BMS. Features. Applications. Functional Diagram. Pinout. CMOS Hex Buffer. FN3335 Rev 0.00 Page 1 of 8. December FN3335 Rev 0.

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1 DATASHEET CD503BMS CMOS Hex Buffer CD503BMS is a hex noninverting buffer with 3 state outputs having high sink and source current capability. Two disable controls are provided, one of which controls four buffers and the other controls the remaining two buffers. The CD503BMS is supplied in these 1-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HT H1E HW Features High Voltage Type (0V Rating) 3 State Non-Inverting Type 1 TTL Load Output Drive Capability Output Disable Controls 3 State Outputs FN3335 Rev 0.00 Pin Compatible with Industry Types MM0C97, MC1503, and V, V and 15V Parametric Ratings Maximum Input Current of 1 A at 1V Over Full Package Temperature Range; 0nA at 1V and +5 o C Meets All Requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices Applications 3 State Hex Buffer for Interfacing ICs with Data Buses COS/MOS to TTL Hex Buffer Pinout CD503BMS TOP VIEW Functional Diagram DISABLE A 1 DIS A D VDD DIS B D1 3 Q1 Q1 D D DQ D 5 Q Q D D5 Q5 D3 7 Q3 Q3 VSS 7 9 D Q D 9 Q D Q5 D 1 13 Q DISABLE B 15 VDD = 1 VSS = FN3335 Rev 0.00 Page 1 of

2 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +0V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +0.5V DC Input Current, Any One Input ma Operating Temperature Range to +15 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +150 o C Lead Temperature (During Soldering) o C At Distance 1/1 1/3 Inch (1.59mm 0.79mm) from case for s Maximum Reliability Information Thermal Resistance ja jc Ceramic DIP and FRIT Package o C/W 0 o C/W Flatpack Package o C/W 0 o C/W Maximum Package Power Dissipation (PD) at +15 o C For TA = - to +0 o C (Package Type D, F, K) mW For TA = +0 o C to +15 o C (Package Type D, F, K).... Derate Linearity at 1mW/ o C to 00mW Device Dissipation per Output Transistor mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND 1 +5 o C - A +15 o C - 00 A VDD = 1V, VIN = VDD or GND A Input Leakage Current IIL VIN = VDD or GND VDD = o C -0 - na +15 o C na VDD = 1V na Input Leakage Current IIH VIN = VDD or GND VDD = o C - 0 na +15 o C - 00 na VDD = 1V na Output Voltage VOL15 VDD = 15V, No Load 1,, 3 +5 o C, +15 o C, mv Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1,, 3 +5 o C, +15 o C, V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V 1 +5 o C.1 - ma Output Current (Sink) IOL VDD = V, VOUT = 0.5V 1 +5 o C ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +5 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1 +5 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1 +5 o C - -. ma Output Current (Source) IOH VDD = V, VOUT = 9.5V 1 +5 o C - -. ma Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +5 o C - -. ma N Threshold Voltage VNTH VDD = V, ISS = - A 1 +5 o C V P Threshold Voltage VPTH VSS = 0V, IDD = A 1 +5 o C 0.7. V Functional F VDD =.V, VIN = VDD or GND 7 +5 o C VOH > VOL < V VDD = 0V, VIN = VDD or GND 7 +5 o C VDD/ VDD/ VDD = 1V, VIN = VDD or GND A +15 o C VDD = 3V, VIN = VDD or GND B - Input Voltage Low VIL VDD = 5V, VOH >.5V, VOL < 0.5V 1,, 3 +5 o C, +15 o C, V (Note ) Input Voltage High (Note ) VIH VDD = 5V, VOH >.5V, VOL < 0.5V 1,, 3 +5 o C, +15 o C, V Input Voltage Low (Note ) Input Voltage High (Note ) Tri-State Output Leakage Tri-State Output Leakage VIL VIH IOZL IOZH VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VIN = VDD or GND VOUT = VDD 1. All voltages referenced to device GND, 0% testing being implemented.. Go/No Go test with limits applied to inputs. 1,, 3 +5 o C, +15 o C, - - V 1,, 3 +5 o C, +15 o C, V VDD = 0V 1 +5 o C A +15 o C -1 - A VDD = 1V A VDD = 0V 1 +5 o C - 0. A +15 o C - 1 A VDD = 1V A 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. FN3335 Rev 0.00 Page of

3 TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Propagation Delay TPHL VDD = 5V, VIN = VDD or GND (Note 1, ) Propagation Delay TPLH VDD = 5V, VIN = VDD or GND (Note 1, ) Propagation Delay3 State Propagation Delay3 State TPHZ TPZH TPZL TPLZ VDD = 5V, VIN = VDD or GND (Note, 3) VDD = 5V, VIN = VDD or GND (Note, 3) Transition Time TTHL VDD = 5V, VIN = VDD or GND (Note 1, ) Transition Time TTLH VDD = 5V, VIN = VDD or GND (Note 1, ) 1. CL = 50pF, RL = 00K, Input TR, TF < 0ns.. - and +15 o C limits guaranteed, 0% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 0ns. GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +5 o C - 1 ns, o C, ns 9 +5 o C ns, o C, ns 9 +5 o C - 10 ns, o C, ns 9 +5 o C - 10 ns, o C, ns 9 +5 o C - 70 ns, o C, ns 9 +5 o C - 90 ns, o C, ns TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1, -, +5 o C - 1 A +15 o C - 30 A VDD = V, VIN = VDD or GND 1, -, +5 o C - A +15 o C - 0 A VDD = 15V, VIN = VDD or GND 1, -, +5 o C - A +15 o C - A Output Voltage VOL VDD = 5V, No Load 1, +5 o C, +15 o C, mv Output Voltage VOL VDD = V, No Load 1, +5 o C, +15 o C, mv Output Voltage VOH VDD = 5V, No Load 1, +5 o C, +15 o C, V Output Voltage VOH VDD = V, No Load 1, +5 o C, +15 o C, V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.V 1, +15 o C ma -. - ma Output Current (Sink) IOL VDD = V, VOUT = 0.5V 1, +15 o C 3. - ma ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, +15 o C ma ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1, +15 o C ma ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1, +15 o C ma ma Output Current (Source) IOH VDD = V, VOUT = 9.5V 1, +15 o C ma ma Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, +15 o C - -. ma ma FN3335 Rev 0.00 Page 3 of

4 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Input Voltage Low VIL VDD = V, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, V Input Voltage High VIH VDD = V, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, V Propagation Delay TPHL VDD = V 1,, 3 +5 o C - 50 ns VDD = 15V 1,, 3 +5 o C - 35 ns Propagation Delay TPLH VDD = V 1,, 3 +5 o C - 70 ns VDD = 15V 1,, 3 +5 o C - 50 ns Propagation Delay TPHZ VDD = V 1,, +5 o C - 0 ns TPZH VDD = 15V 1,, +5 o C - 50 ns Propagation Delay TPZL VDD = V 1,, +5 o C - 0 ns TPLZ VDD = 15V 1,, +5 o C - 70 ns Transition Time TTHL VDD = V 1,, 3 +5 o C - 0 ns VDD = 15V 1,, 3 +5 o C - 5 ns Transition Time TTLH VDD = V 1,, 3 +5 o C - 5 ns VDD = 15V 1,, 3 +5 o C - 35 ns Input Capacitance CIN Any Inputs 1, +5 o C pf 1. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 00K, Input TR, TF < 0ns.. CL = 50pF, RL = 1K, Input TR, TF < 0ns. TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 0V, VIN = VDD or GND 1, +5 o C A N Threshold Voltage VNTH VDD = V, ISS = - A 1, +5 o C V N Threshold Voltage VTN VDD = V, ISS = - A 1, +5 o C - 1 V Delta P Threshold Voltage VTP VSS = 0V, IDD = A 1, +5 o C 0.. V P Threshold Voltage VTP VSS = 0V, IDD = A 1, +5 o C - 1 V Delta Functional F VDD = 1V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 1 +5 o C VOH > VDD/ Propagation Delay Time TPHL TPLH 1. All voltages referenced to device GND.. CL = 50pF, RL = 00K, Input TR, TF < 0ns. VOL < VDD/ VDD = 5V 1,, 3, +5 o C x +5 o C Limit 3. See Table for +5 o C limit.. Read and Record V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 o C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD 0. A Output Current (Sink) IOL5 0% x Pre-Test Reading Output Current (Source) IOH5A 0% x Pre-Test Reading FN3335 Rev 0.00 Page of

5 TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-3 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 0% 500 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 0% 500 1, 7, 9, Deltas Final Test 0% 500, 3, A, B,, 11 Group A Sample ,, 3, 7, A, B, 9,, 11 Group B Subgroup B-5 Sample ,, 3, 7, A, B, 9,, 11, Deltas Subgroups 1,, 3, 9,, 11 Subgroup B- Sample , 7, 9 Group D Sample ,, 3, A, B, 9 Subgroups 1, 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-3 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup , 7, 9 Table 1, 9 Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V -0.5V Static Burn-In 1 (Note 1) Static Burn-In (Note 1) Dynamic Burn- In (Note 1) Irradiation (Note ) 3, 5, 7, 9, 11, 13 1,,,,,, 1, 1, 15 3, 5, 7, 9, 11, 13 1,,,,, 1, ,, , 5, 7, 9, 11, 13,,,, 1, 1 3, 5, 7, 9, 11, 13 1,,,,, 1, 1-1 OSCILLATOR 50kHz 5kHz 1. Each pin except VDD and GND will have a series resistor of K 5%, VDD = 1V 0.5V. Each pin except VDD and GND will have a series resistor of 7K 5%; Group E, Subgroup, sample size is dice/wafer, 0 failures, VDD = V 0.5V FN3335 Rev 0.00 Page 5 of

6 Logic Diagram DI * (,,, 1, 1) VDD TRUTH TABLE DN DIS A (B) Qn DIS A (B) * 1 (15) DISABLE TO OTHER BUFFERS VSS QN 3 (5, 7, 9, 11, 13) VDD X 1 High Z X = Don t Care * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS Typical Performance Characteristics FIGURE 1. LOGIC DIAGRAM OF 1 TO IDENTICAL BUFFERS OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V V 5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -9 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) - GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -7-15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 3. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -9 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FN3335 Rev 0.00 Page of

7 Typical Performance Characteristics (Continued) PROPAGATION DELAY TIME (tplh, tphl) (ns) tplh tphl VDD = 5V VDD = V VDD = 15V TRANSITION TIME (tthl, ttlh) (ns) V (ttlh) 5V (tthl) V (ttlh) 15V (ttlh) V (tthl) 15V (tthl) LOAD CAPACITANCE (CL) (pf) LOAD CAPACITANCE (CL) (pf) FIGURE. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE POWER DISSIPATION (PD) ( W) K 1K 0 VDD = 15V VDD = V VDD = 5V CL = 50pF CL = 15pF 1 3 FREQUENCY (f) (khz) tr = tf = 0ns FIGURE. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY FN3335 Rev 0.00 Page 7 of

8 Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch). METALLIZATION: Thickness: 11kÅ 1kÅ, AL. PASSIVATION:.kÅ - 15.kÅ, Silane BOND PADS: 0.00 inches X 0.00 inches MIN DIE THICKNESS: inches inches Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3335 Rev 0.00 Page of

DATASHEET CD4504BMS. Pinout. Features. Functional Diagram. Description. CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

DATASHEET CD4504BMS. Pinout. Features. Functional Diagram. Description. CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation DATASHEET CD454BMS CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation FN3336 Rev. Features Pinout High Voltage Type (2V Rating) Independence of Power Supply Sequence Considerations