EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

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1 EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

2 CD49BMS December 199 Features High-Voltage Type (V Rating) Medium Speed Operation: 8MHz (Typ.) at CL = 5pF and VDD - VSS = 1V Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times Preset Enable and Individual Jam Inputs Provided Binary or Decade Up/Down Counting BCD Outputs in Decade Mode 1% Tested for Maximum Quiescent Current at V 5V, 1V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 1nA at 18V and +5 o C Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - V at VDD = 1V -.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards No. 13B, Standard Specifications for Description of B Series CMOS Device s Applications Programmable Binary and Decade Counting/Frequency Synthesizers-BCD Output Analog to Digital and Digital to Analog Conversion Up/Down Binary Counting Difference Counting Magnitude and Sign Generation Up/Down Decade Counting CMOS Presettable Up/Down Counter Description CD49BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ), BINARY/DECADE, UP/DOWN, PRESET, and four individual JAM signals. Q1, Q, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET- signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRE-SET signals are low. Advancement is inhibited when the CARRY-IN or PRESET signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallelclocking or a ripple-clocking arrangement as shown in Figure 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD49BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W Pinout PRESET Q4 1 CD49BMS TOP VIEW VDD CLOCK Functional Diagram PRESET JAM INPUTS VDD CARRY IN (CLOCK ) 5 6 Q1 JAM 4 JAM Q3 JAM 3 BINARY/ DECADE 9 11 Q CARRY IN Q JAM Q UP/DOWN 1 Q3 14 BUFFERED OUTPUTS CARRY OUT VSS UP/DOWN BINARY/DECADE CLOCK 15 7 Q4 8 VSS CARRY OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Corporation File Number 334

3 Specifications CD49BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +.5V DC Input Current, Any One Input ±1mA Operating Temperature Range o C to +15 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +15 o C Lead Temperature (During Soldering) o C At Distance 1/16 ± 1/3 Inch (1.59mm ±.79mm) from case for 1s Maximum Reliability Information Thermal Resistance θ ja θ jc Ceramic DIP and FRIT Package o C/W o C/W Flatpack Package o C/W o C/W Maximum Package Power Dissipation (PD) at +15 o C For TA = -55 o C to +1 o C (Package Type D, F, K) mW For TA = +1 o C to +15 o C (Package Type D, F, K).....Derate Linearity at 1mW/ o C to mw Device Dissipation per Output Transistor mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE MIN LIMITS Supply Current IDD VDD = V, VIN = VDD or GND 1 +5 o C - 1 µa MAX UNITS +15 o C - 1 µa VDD = 18V, VIN = VDD or GND 3-55 o C - 1 µa Input Leakage Current IIL VIN = VDD or GND VDD = 1 +5 o C -1 - na +15 o C -1 - na VDD = 18V 3-55 o C -1 - na Input Leakage Current IIH VIN = VDD or GND VDD = 1 +5 o C - 1 na +15 o C - 1 na VDD = 18V 3-55 o C - 1 na Output Voltage VOL15 VDD = 15V, No Load 1,, 3 +5 o C, +15 o C, -55 o C - 5 mv Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1,, 3 +5 o C, +15 o C, -55 o C V Output Current (Sink) IOL5 VDD = 5V, VOUT =.4V 1 +5 o C.53 - ma Output Current (Sink) IOL1 VDD = 1V, VOUT =.5V 1 +5 o C ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +5 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +5 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1 +5 o C ma Output Current (Source) IOH1 VDD = 1V, VOUT = 9.5V 1 +5 o C ma Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +5 o C ma N Threshold Voltage VNTH VDD = 1V, ISS = -1µA 1 +5 o C V P Threshold Voltage VPTH VSS = V, IDD = 1µA 1 +5 o C.7.8 V Functional F VDD =.8V, VIN = VDD or GND 7 +5 o C VOH > VDD = V, VIN = VDD or GND 7 +5 o C VDD/ Input Voltage Low (Note ) Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VDD = 18V, VIN = VDD or GND 8A +15 o C VDD = 3V, VIN = VDD or GND 8B -55 o C VOL < VDD/ VIL VDD = 5V, VOH > 4.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, -55 o C V VIH VDD = 5V, VOH > 4.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, -55 o C V VIL VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 1. All voltages referenced to device GND, 1% testing being implemented.. Go/No Go test with limits applied to inputs. 1,, 3 +5 o C, +15 o C, -55 o C - 4 V 1,, 3 +5 o C, +15 o C, -55 o C 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is.5v max. V 7-799

4 Specifications CD49BMS TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, ) Clock To Q Output Clock To Carry Out Preset Enable To Q Preset Enable To Carry- Out Carry-In To Carry-Out Transition Time Q Output Maximum Clock Input Frequency NOTES: TPHL1 TPLH1 TPHL TPLH TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TTHL TTLH 1. VDD = 5V, CL = 5pF, RL = K GROUP A SUBGROUPS TEMPERATURE MIN LIMITS MAX VDD = 5V, VIN = VDD or GND 9 +5 o C - 5 ns UNITS 1, o C, -55 o C ns VDD = 5V, VIN = VDD or GND 9 +5 o C - 56 ns 1, o C, -55 o C ns VDD = 5V, VIN = VDD or GND 9 +5 o C - 47 ns 1, o C, -55 o C ns VDD = 5V, VIN = VDD or GND 9 +5 o C - 64 ns 1, o C, -55 o C ns VDD = 5V, VIN = VDD or GND 9 +5 o C - 34 ns 1, o C, -55 o C ns VDD = 5V, VIN = VDD or GND 9 +5 o C - ns 1, o C, -55 o C - 7 ns FCL VDD = 5V, VIN = VDD or GND 9 +5 o C - MHz. -55 o C and +15 o C limits guaranteed, 1% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS 1, o C, -55 o C MHz PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1, -55 o C, +5 o C - 5 µa MIN MAX UNITS +15 o C - 15 µa VDD = 1V, VIN = VDD or GND 1, -55 o C, +5 o C - 1 µa +15 o C - 3 µa VDD = 15V, VIN = VDD or GND 1, -55 o C, +5 o C - 1 µa Output Voltage VOL VDD = 5V, No Load 1, +5 o C, +15 o C, -55 o C Output Voltage VOL VDD = 1V, No Load 1, +5 o C, +15 o C, -55 o C Output Voltage VOH VDD = 5V, No Load 1, +5 o C, +15 o C, -55 o C Output Voltage VOH VDD = 1V, No Load 1, +5 o C, +15 o C, -55 o C +15 o C - 6 µa - 5 mv - 5 mv V V Output Current (Sink) IOL5 VDD = 5V, VOUT =.4V 1, +15 o C.36 - ma -55 o C.64 - ma Output Current (Sink) IOL1 VDD = 1V, VOUT =.5V 1, +15 o C.9 - ma -55 o C ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, +15 o C.4 - ma -55 o C 4. - ma Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, +15 o C ma -55 o C ma 7-8

5 Specifications CD49BMS Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1, +15 o C ma -55 o C - -. ma Output Current (Source) IOH1 VDD = 1V, VOUT = 9.5V 1, +15 o C ma -55 o C ma Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, +15 o C ma Input Voltage Low VIL VDD = 1V, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, -55 o C Input Voltage High VIH VDD = 1V, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, -55 o C Q Output Carry Output Preset Enable To Q Preset Enable To Carry- Out Carry In To Carry Out Transition Time Maximum Clock Input Frequency Minimum Data Setup Time Note 4 Clock Rise And Fall Time Note 5 Minimum Clock Pulse Width Minimum Carry In Setup Time Note 6 Minimum Carry Input Hold Time Note 6 Minimum Preset Enable Removal Time Note 4 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE TPHL1 TPLH1 TPHL TPLH TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TTHL TTLH -55 o C ma - 3 V 7 - V VDD = 1V 1,, 3 +5 o C - 4 ns VDD = 15V 1,, 3 +5 o C - 18 ns VDD = 1V 1,, 3 +5 o C - 6 ns VDD = 15V 1,, 3 +5 o C - 19 ns VDD = 1V 1,, 3 +5 o C - ns VDD = 15V 1,, 3 +5 o C - 16 ns VDD = 1V 1,, 3 +5 o C - 9 ns VDD = 15V 1,, 3 +5 o C - 1 ns VDD = 1V 1,, 3 +5 o C - 14 ns VDD = 15V 1,, 3 +5 o C - 1 ns VDD = 1V 1,, 3 +5 o C - 1 ns VDD = 15V 1,, 3 +5 o C - 8 ns FCL VDD = 1V 1,, 3 +5 o C 4 - MHz VDD = 15V 1,, 3 +5 o C MHz TS VDD = 5V 1,, 3 +5 o C - 34 ns TRCL TFCL VDD = 1V 1,, 3 +5 o C - 14 ns VDD = 15V 1,, 3 +5 o C - 1 ns VDD = 5V 1,, 3 +5 o C - 15 µs VDD = 1V 1,, 3 +5 o C - 15 µs VDD = 15V 1,, 3 +5 o C - 15 µs TW VDD = 5V 1,, 3 +5 o C - 18 ns VDD = 1V 1,, 3 +5 o C - 9 ns VDD = 15V 1,, 3 +5 o C - 6 ns TS VDD = 5V 1,, 3 +5 o C - ns VDD = 1V 1,, 3 +5 o C - 7 ns VDD = 15V 1,, 3 +5 o C - 6 ns TH VDD = 5V 1,, 3 +5 o C - 5 ns VDD = 1V 1,, 3 +5 o C - 3 ns VDD = 15V 1,, 3 +5 o C - 5 ns TREM VDD = 5V 1,, 3 +5 o C - ns VDD = 1V 1,, 3 +5 o C - 11 ns VDD = 15V 1,, 3 +5 o C - 8 ns MIN LIMITS MAX UNITS 7-81

6 Specifications CD49BMS Minimum Preset Enable Pulse Width TW VDD = 5V 1,, 3 +5 o C - 13 ns VDD = 1V 1,, 3 +5 o C - 7 ns VDD = 15V 1,, 3 +5 o C - 5 ns Input Capacitance CIN Any Input 1, +5 o C pf NOTES: 1. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 5pF, RL = K, Input TR, TF < ns. 4. From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge. 5. If more than one unit is cascaded in the parallel clocked application, tr CL should be made the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load. This measurement was made with a decoupling capacitor (>1µF) between VDD and VSS. 6. From Carry In to Clock Edge. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN LIMITS MAX UNITS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN LIMITS Supply Current IDD VDD = V, VIN = VDD or GND 1, 4 +5 o C - 5 µa N Threshold Voltage VNTH VDD = 1V, ISS = -1µA 1, 4 +5 o C V N Threshold Voltage Delta VTN VDD = 1V, ISS = -1µA 1, 4 +5 o C - ±1 V P Threshold Voltage VTP VSS = V, IDD = 1µA 1, 4 +5 o C..8 V P Threshold Voltage Delta VTP VSS = V, IDD = 1µA 1, 4 +5 o C - ±1 V Functional F VDD = 18V, VIN = VDD or GND 1 +5 o C VOH > VDD = 3V, VIN = VDD or GND VDD/ Time NOTES: TPHL TPLH 1. All voltages referenced to device GND.. CL = 5pF, RL = K, Input TR, TF < ns 3. See Table for +5 o C limit. 4. Read and Record MAX VOL < VDD/ VDD = 5V 1,, 3, 4 +5 o C x +5 o C Limit UNITS V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI- IDD ± 1.µA Output Current (Sink) IOL5 ± % x Pre-Test Reading Output Current (Source) IOH5A ± % x Pre-Test Reading 7-8

7 Specifications CD49BMS CONFORMANCE GROUP TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 1% 54 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 1% 54 1, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 1% 54 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 54 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 1% 54 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 54 1, 7, 9, Deltas Final Test 1% 54, 3, 8A, 8B, 1, 11 Group A Sample 55 1,, 3, 7, 8A, 8B, 9, 1, 11 Group B Subgroup B-5 Sample 55 1,, 3, 7, 8A, 8B, 9, 1, 11, Deltas Subgroups 1,, 3, 9, 1, 11 Subgroup B-6 Sample 55 1, 7, 9 Group D Sample 55 1,, 3, 8A, 8B, 9 Subgroups 1, 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and. CONFORMANCE GROUPS MIL-STD-883 METHOD TABLE 7. TOTAL DOSE IRRADIATION TEST READ AND RECORD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 55 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V ± -.5V Static Burn-In 1 Note 1 Static Burn-In Note 1 Dynamic Burn- In Note 1 Irradiation Note NOTE:, 6, 7, 11, 14 1, 3-5, 8-1, 1, 13, 15, 6, 7, 11, , 3-5, 9, 1, 1, 13, 15, kHz OSCILLATOR - 1, 3-5, 8, 1, 13 9, 1, 16, 6, 7, 11, , 6, 7, 11, , 3-5, 9, 1, 1, 13, 15, Each pin except VDD and GND will have a series resistor of 1K ± 5%, VDD = 18V ±.5V. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup, sample size is 4 dice/wafer, failures, VDD = 1V ±.5V 5kHz 7-83

8 BINARY/ DECADE * 9 PRESET * 1 * * 4 J1 1 J * * 13 J3 3 J4 Logic Diagram CARRY IN * 5 CLOCK PE J TE1 Q1 F/F1 Q1 CL PE J TE Q F/F Q CL PE J TE3 Q3 F/F3 Q3 CL PE J TE4 Q4 F/F4 Q4 CL 7 CARRY OUT 7-84 UP/DOWN * 1 CLOCK * 15 6 Q 11 Q 14 Q3 Q4 CD49BMS TRUTH TABLE FUNCTION TABLE VDD CLOCK TE PE J Q Q CONTROL INPUT LOGIC LEVEL ACTION *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS PE TE J Q Q X X 1 BIN/DEC (B/D) 1 X Q Q UP/DOWN (U/D) X X 1 1 Preset Enable (PE) 1 1 X Q Q NC CARRY IN (CI) (CLOCK ) Binary Count Decade Count Up Count Down Count Jam In No Jam No Counter Advance at POS Clock Transition Advance Counter at POS Clock Transition X 1 X Q Q NC X = Don t Care FIGURE 1.

9 CD49BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V 1V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT LOW (SINK) CURRENT (IOL) (ma) V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 1V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -1V -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -1V -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS TRANSITION TIME (tthl, ttlh) (ns) 15 SUPPLY VOLTAGE (VDD) = 5V 1 1V 15V LOAD CAPACITANCE (CL) (pf) PROPAGATION DELAY TIME (tphl, tplh) (ns) 3 SUPPLY VOLTAGE (VDD) = 5V 1V 1 15V LOAD CAPACITANCE (CL) (pf) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (Q OUTPUT) 7-85

10 CD49BMS Typical Performance Characteristics (Continued) PROPAGATION DELAY TIME (t PHL, t PLH ) (ns) V SUPPLY VOLTAGE (VDD) = 5V 1V LOAD CAPACITANCE (CL) (pf) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CARRY OUTPUT) POWER DISSIPATION (PD) (µw) SUPPLY VOLTAGE (VDD) = 15V 1V 1V CL = 5pF CL = 15pF CLOCKFREQUENCY (fcl) (khz) FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY 5V Timing Diagrams CLOCK (CL) CARRY IN (CL ) UP/DOWN BINARY/ DECADE PRESET J1 J J3 J4 Q1 Q Q3 Q4 CARRY OUT COUNT The CD49BMS CLOCK and UP/DOWN inputs are used directly in most applications. In applications where CLOCK UP and CLOCK DOWN inputs are provided, conversion to the CD49BMS CLOCK and UP/DOWN inputs can easily be realized by use of the circuit in Figure 11. CD49BMS changes count on positive transitions of CLOCK UP or CLOCK DOWN inputs. For the gate configuration in Figure 1, when counting up the CLOCK DOWN input must be maintained high and conversely when counting down the CLOCK UP input must be maintained high. CLOCK UP CLOCK DOWN 1 CD411 QUAD INPUT NAND GATE VDD UP/DOWN CLOCK FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN INPUT SIGNALS TO CLOCK AND UP/DOWN INPUT SIGNALS 7-86

11 CD49BMS Timing Diagrams (Continued) CLOCK (CL) CARRY IN (CL ) UP/DOWN BINARY/ DECADE PRESET J1 J J3 J4 Q1 Q Q3 Q4 CARRY OUT COUNT FIGURE 1. TIMING DIAGRAM-DECADE MODE PARALLEL CLOCKING UP/DOWN PRESET UP/D PE J1 J J3 J4 UP/D PE J1 J J3 J4 UP/D PE J1 J J3 J4 CI CD49 CO CI CD49 CO CI CD49 CO * B/D CL Q1 Q Q3 Q4 B/D CL Q1 Q Q3 Q4 B/D CL Q1 Q Q3 Q4 CLOCK BINARY/ DECADE *CARRY OUT LINES AT THE ND, 3RD, ETC, STAGES MAY HAVE A NEG- ATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL DELAYS OF DIFFERENT CD49BMS IC S. THESE NEGATIVE GOING GLITCHES DO NOT AFFECT PROPER CD49BMS OPERATION. HOW- EVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF S OR COUNTERS, THE CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL USING A -INPUT OR GATE SUCH AS CD471BMS. FIGURE 13. CASCADING COUNTER PACKAGES All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site 87

12 CD49BMS Timing Diagrams (Continued) RIPPLE CLOCKING UP/DOWN PRESET UP/D PE J1 J J3 J4 UP/D PE J1 J J3 J4 UP/D PE J1 J J3 J4 CI CD49 CO CI CD49 CO CI CD49 CO B/D CL Q1 Q Q3 Q4 B/D CL Q1 Q Q3 Q4 B/D CL Q1 Q Q3 Q4 CLOCK 1/4 CD471B 1/4 CD471B BINARY/ DECADE RIPPLE CLOCKING MODE: THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE, THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON- NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI GROUNDED. FIGURE 13. CASCADING COUNTER PACKAGES (Continued) Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1-3 inch) METALLIZATION: Thickness: 11kÅ 14kÅ, AL. PASSIVATION: BOND PADS: DIE THICKNESS: 1.4kÅ kÅ, Silane.4 inches X.4 inches MIN.198 inches -.18 inches 7-88