MC14040B. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648

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1 The MC14040B 12 stage binary counter is cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 12 stages of ripple carry binary counter. The device advances the count on the negative going edge of the clock pulse. Applicatio include time delay circuits, counter controls, and frequency driving circuits. Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range Common Reset Line Pin for Pin Replacement for CD4040B MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol Parameter Value Unit VDD DC Supply Voltage Range 0.5 to V Vin, Vout Iin, Iout PD Input or Output Voltage Range (DC or Traient) Input or Output Current (DC or Traient) per Pin Power Dissipation, per Package (Note 3.) 0.5 to VDD V ±10 ma 500 mw TA Ambient Temperature Range 55 to +125 C Tstg Storage Temperature Range 65 to +150 C TL Lead Temperature (8 Second Soldering) 260 C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/c From 65C To 125C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, Vin and Vout should be cotrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. A WL, L YY, Y WW, W PDIP 16 P SUFFIX CASE 648 SOIC 16 D SUFFIX CASE 751B TSSOP 16 DT SUFFIX CASE 948F SOEIAJ 16 F SUFFIX CASE 966 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION MARKING DIAGRAMS Device Package Shipping MC14040BCP PDIP /Box MC14040BD SOIC /Box MC14040BDR2 SOIC /Tape & Reel MC14040BCP AWLYYWW 14040B AWLYWW 16 MC14040B ALYW MC14040BDT TSSOP 16 96/Rail B ALYW MC14040BF SOEIAJ 16 See Note 1. MC14040BFEL SOEIAJ 16 See Note For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2001 September, 2001 Rev. 5 1 Publication Order Number: MC14040B/D

2 PIN ASSIGNMENT TRUTH TABLE Clock Reset Output State 0 No Change 0 Advance to next state X 1 All Outputs are low X = Don t Care LOGIC DIAGRAM 2

3 ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) ÎÎ 55C 25C ÎÎ 125C Î VDD Characteristic Î Symbol Vdc Min MaxÎ Min Typ (4.)Î Max Min Max Unit Î Output Voltage 0 Level Î VOL Î 0 Î Vdc Î Vin = VDD or Î 1 Level VOH Î Vin = 0 or VDD Î ÎÎ Î Î 9.95 Vdc Input Voltage 0 Level VIL Vdc Î (VO = 4.5 or 0.5 Vdc) 5.0 Î (VO = 9.0 or 1.0 Vdc) Î Î (VO O = 13.5 or 1.5 Vdc) Level VIH Vdc Î (VO = 0.5 or 4.5 Vdc) 5.0 Î (VO = 1.0 or 9.0 Vdc) Î Î 7.0 (VO = 1.5 or 13.5 Vdc) Output Drive Current IOH madc Î (VOH = 2.5 Vdc) Source Î Î 1.7 Î (VOH = 4.6 Vdc) Î (VOH = 9.5 Vdc) Î (VOH = 13.5 Vdc) Î Î 2.4 Î (VOL = 0.4 Vdc) Sink Î IOL 5.0 Î (VOL = 0.5 Vdc) Î Î 0.9 madc (VOL = 1.5 Vdc) ÎÎ Î Input Current Iin 15 ± 0.1 ± ± 0.1 ± 1.0 µadc Input Capacitance Cin Î (Vin = 0) Î Î 5.0Î 7.5 Î pf Î Quiescent Current Î IDD 5.0 Î (Per Package) Î Î 0.010Î µadc Total Supply Current (5.) (6.) IT 5.0 IT = (0.42 µa/khz) f + IDD µadc Î (Dynamic plus Quiescent, 10 ÎÎ IT = (0.85 µa/khz) f + IDD Per Package) 15 Î IT = (1.43 µa/khz) f + IDD (CL = 50 pf on all outputs, all Î buffers switching) 4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 5. The formulas given are for the typical characteristics only at 25C. 6. To calculate total supply current at loads other than 50 pf: IT(CL) = IT(50 pf) + (CL 50) Vfk where: IT is in µa (per package), CL in pf, V = (VDD VSS) in volts, f in khz is input frequency, and k =

4 SWITCHING CHARACTERISTICS (7.) (CL = 50 pf, TA = 25C) Î VDD Î Î Characteristic Symbol Î Vdc Min Typ (8.) Max Î Î Unit Output Rise and Fall Time ttlh, TTLH, TTHL = (1.5 /pf) CL + 25 tthl TTLH, TTHL = (0.75 /pf) CL ÎÎ 10 Î Î 50 Î 100 TTLH, TTHL = (0.55 /pf) CL Propagation Delay Time tplh, Clock to Q1 Î tphl tphl, tplh = (1.7 /pf) CL ÎÎ 5.0 Î Î 260 Î 520 tphl, tplh = (0.66 /pf) CL tphl, tplh = (0.5 /pf) CL + 95 ÎÎ 15 Î Î 80 Î 160 Clock to Q12 Î tphl, tplh = (1.7 /pf) CL ÎÎ 5.0 Î Î 1625 Î 3250 tphl, tplh = (0.66 /pf) CL tphl, tplh = (0.5 /pf) CL ÎÎ 15 Î Î 500 Î 1000 Propagation Delay Time ÎÎ tphl Î Î Î Reset to Qn Î tphl = (1.7 /pf) CL tphl = (0.86 /pf) CL ÎÎ 10 Î Î 155 Î 310 tphl = (0.5 /pf) CL Î Clock Pulse Width Î twh Î Î Î Î 15 Î 115 Î 38 Î Clock Pulse Frequency ÎÎ fcl Î 5.0 Î Î 2.1 Î 1.5 MHz Î 15 Î Î 10.0 Î 4.5 Clock Rise and Fall Time ÎÎ ttlh, tthl Î Î 5.0 Î 10 Î No Limit 15 Reset Pulse Width twh Î 10 Î 360 Î 120 Î Reset Removal Time Î trem Î Î Î Î 15 Î 30 Î 15 Î 7. The formulas given are for the typical characteristics only at 25C. 8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 4

5 µ µ Figure 1. Power Dissipation Test Circuit and Waveform Figure 2. Switching Time Test Circuit and Waveforms Figure 3. Timing Diagram 5

6 APPLICATIONS INFORMATION TIME BASE GENERATOR A 60 Hz sinewave obtained through a 1.0 Megohm resistor connected directly to a standard 120 Vac power line is applied to the clock input of the MC14040B. By selecting outputs Q5, Q10, Q11, and Q12 division by 3600 is accomplished. The MC14012B decodes the counter outputs, produces a single output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute. NOTE: Ground MUST be isolated by a traformer or opto isolator for safety reaso. Figure 4. Time Base Generator PACKAGE DIMENSIONS H A G B F C S K D 16 PL PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE R T J L M 6

7 PACKAGE DIMENSIONS T G A D 16 PL K B C SOIC 16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B 05 ISSUE J P 8 PL M R X 45 J F e Z D b E A HE A1 SOEIAJ 16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE ISSUE O VIEW P M LE L DETAIL P Q1 c 7

8 PACKAGE DIMENSIONS T L PIN 1 IDENT. D 2X L/2 C 16X K REF A V G TSSOP 16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F 01 ISSUE O B U H N N J J1 F DETAIL E DETAIL E K K1 ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N M W ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@oemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 8 MC14040B/D