MC14541B. Programmable Timer

Transcription

1 MC44 Programmable Timer The MC44 programmable timer coists of a stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power on reset circuit, and output control logic. Timing is initialized by turning on power, whereupon the power on reset is enabled and initializes the counter, within the specified range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The stage counter divides the oscillator frequency (fosc) with the nth stage frequency being fosc/2n. vailable Outputs 28, 2, 2 or 2 Increments on Positive Edge Clock Traitio uilt in Low Power RC Oscillator (± 2% accuracy over temperature range and ± 2% supply and ± % over processing at < khz) Oscillator May e ypassed if External Clock Is vailable (pply external clock to Pin ) External Master Reset Totally Independent of utomatic Reset Operation Operates as 2n Frequency Divider or Single Traition Timer / Select Provides Output Logic Level Flexibility Reset (auto or master) Disables Oscillator During Resetting to Provide No ctive Power Dissipation Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times utomatic Reset Initializes ll Counters On Power Up Supply Voltage Range = to 8 with uto Reset Supply Voltage Range = Disabled (Pin = ) Supply Voltage Range = 8. to 8 with uto Reset Supply Voltage Range = Enabled (Pin = ) MXIMUM RTINGS (Voltages Referenced to ) (Note 2.) Symbol Parameter Value Unit DC Supply Voltage Range. to +8. V Vin, Vout Input or Output Voltage Range (DC or Traient). to +. V Iin Input Current (DC or Traient) ± (per Pin) m Iout Output Current (DC or Traient) ±4 (per Pin) m PD Power Dissipation, per Package (Note.) mw T mbient Temperature Range to +2 C Tstg Storage Temperature Range to + C TL Lead Temperature (8 Second Soldering) 2 C 2. Maximum Ratings are those values beyond which damage to the device may occur.. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ C From C To 2 C WL, L YY, Y WW, W PDIP 4 P SUFFIX CSE 4 SOIC 4 D SUFFIX CSE 7 TSSOP 4 DT SUFFIX CSE 48G 4 ORDERING INFORMTION KING DIGRMS Device Package Shipping MC44CP PDIP 4 2/ox MC44D SOIC 4 /Rail MC44DR2 SOIC 4 2/Tape & Reel MC44DT TSSOP 4 /Rail MC44DTR2 TSSOP 4 2/Tape & Reel MC44F SOEIJ 4 See Note. MC44FEL SOEIJ 4 See Note.. For ordering information on the EIJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, Vin and Vout should be cotrained to the range (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open MC44CP WLYYWW 44 WLYWW SOEIJ 4 F SUFFIX CSE = ssembly Location = Wafer Lot = Year = Work Week 4 4 LYW MC44 LYW Semiconductor Components Industries, LLC, 2 ugust, 2 Rev Publication Order Number: MC44/D

2 MC44 PIN SSIGNMENT Rtc R / SEL 7 8 = NO CONNECTION ELECTRICL CHRCTERISTICS (Voltages Referenced to ) Characteristic Output Voltage Vin = or Vin = or Level Level Input Voltage Level (VO = 4. or. ) (VO =. or. ) (VO = or. ) (VO =. or 4. ) (VO =. or. ) (VO =. or ) Output Drive Current (VOH = 2. ) (VOH =. ) (VOH = ) (VOL =.4 ) (VOL =. ) (VOL =. ) Level Source Sink Symbol VOL VOH VIL VIH IOH C 2 C 2 C Min Max Min Typ (4.) Max Min Max Unit IOL Input Current Iin ±. ±. ±. ±. µdc Input Capacitance (Vin = ) uiescent Current (Pin is High) uto Reset Disabled uto Reset uiescent Current (Pin is low) Supply Current (.) (.) (Dynamic plus uiescent) Cin 7. pf IDD IDDR ID ID = (.4 µ/khz) f + IDD ID = (.8 µ/khz) f + IDD ID = (.2 µ/khz) f + IDD 4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at 2 C.. When using the on chip oscillator the total supply current (in µdc) becomes: IT = ID + 2 f x where ID is in µ, is in pf, in Volts DC, and f in khz. (see Fig. ) Dissipation during power on with automatic reset enabled is typically =.. 2 mdc mdc µdc µdc µdc 48

3 MC44 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHRCTERISTICS (7.) (CL = pf, T = 2 C) Characteristic Symbol Min Typ (8.) Max Unit Output Rise and Fall Time ttlh, tthl = (. /pf) CL + 2 ttlh, tthl = (.7 /pf) CL + 2. ttlh, tthl = (. /pf) CL +. Propagation Delay, Clock to (28 Output) tplh, tphl = (.7 /pf) CL + 4 tplh, tphl = (. /pf) CL + 27 tplh, tphl = (. /pf) CL + 87 Propagation Delay, Clock to (2 Output) tphl, tplh = (.7 /pf) CL + tphl, tplh = (. /pf) CL + 47 tphl, tplh = (. /pf) CL ttlh, tthl tplh tphl tphl tplh Clock Pulse Width twh(cl) Clock Pulse Frequency (% Duty Cycle) fcl Pulse Width twh(r) Master Reset Removal Time trem 7. The formulas given are for the typical characteristics only at 2 C. 8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance µs µs MHz PULSE GENERTOR R / SELECT CL PULSE GENERTOR R / SELECT CL (Rtc ND OUTPUTS RE LEFT OPEN) % % % % DUTY CYCLE % % % tplh % % % ttlh % % tphl tthl Figure. Power Dissipation Test Circuit and Waveform Figure 2. Switching Time Test Circuit and Waveforms 4

4 MC44 EXPNDED LOCK DIGRM 2 Rtc 2 OSC 8 STGE C 28 COUNTER C 8 STGE COUNTER OF 4 MUX 8 UTO POWER ON = PIN 4 = PIN 7 MSTER / SELECT FREUEY SELECTION TLE Number of Counter Stages n Count 2n TRUTH TLE State Pin uto Reset, uto Reset Operating uto Reset Disabled Master Reset, Timer Operational Master Reset On /, Output Initially Low fter Reset Output Initially High fter Reset Mode, Single Cycle Mode Recycle Mode TO CLOCK CIRCUIT INTERNL 2 RTC Figure. Oscillator Circuit Using RC Configuration

5 MC44 TYPICL RC OSCILLTOR CHRCTERISTICS FREUEY DEVITION (%) R TC = kω, C = pf 2 V = V V R S =, f =. V DD = V, T = 2 C R S = 2 kω, f = 7.8 V DD = V, T = 2 C 2 7 T, MIENT TEMPERTURE ( C) Figure 4. RC Oscillator Stability 2 f, OSCILLTOR FREUEY (khz) f S FUTION OF C (RTC = kω) ( = 2 kω) = V f S FUTION OF RTC (C = pf) ( 2RTC).. k k k. m RTC, RESISTE (OHMS).... C, CPCITE (µf) OPERTING CHRCTERISTICS Figure. RC Oscillator Frequency as a Function of Rtc and With uto Reset pin set to a the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a. oth types of reset will result in synchronously resetting all counter stages independent of counter state. uto Reset pin when set to a provides a low power operation. The RC oscillator as shown in Figure will oscillate with a frequency determined by the external RC network i.e., f = 2. Rtc if ( khz f khz) and 2 Rtc where kω The time select inputs ( and ) provide a two bit address to output any one of four counter stages (28, 2, 2 and 2). The 2n counts as shown in the Frequency Selection Table represents the output of the Nth stage of the counter. When is, 2 is selected for both states of. However, when is, normal counting is interrupted and the th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The / select output control pin provides for a choice of output level. When the counter is in a reset condition and / select pin is set to a the output is a, correspondingly when / select pin is set to a the output is a. When the mode control pin is set to a, the selected count is continually tramitted to the output. ut, with mode pin and after a reset condition the flip flop (see Expanded lock Diagram) resets, counting commences, and after 2n counts the flip flop sets which causes the output to change state. Hence, after another 2n counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. DIGITL TIMER PPLICTION t INPUT Rtc R S R / t + t N.C. OUTPUT When Master Reset () receives a positive pulse, the internal counters and latch are reset. The output goes high and remai high until the selected (via and ) number of clock pulses are counted, the output then goes low and remai low until another input pulse is received. This one shot is fully retriggerable and as accurate as the input frequency. n external clock can be used (pin is the clock input, pi and 2 are outputs) if additional accuracy is needed. Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time output will be high.