Low Power Consumption IPS009BL9_BL9A_BLAA AT Cut 32KHz SPXO

Transcription

1 Description IPS009BL9, IPS009BL9A and is the specific SPXO IC for achieving 32KHz output by divide, corresponding to the fundamental crystal from 14MHZ to 27MHz and MHz corresponding to each IC. The power consumption of these IC is quite low, so IPS009BL9, IPS009BL9A and suit for mobile application. Features Divide function : 1/512 or 1/1024 Crystal frequency : 14MHz to 27MHz or MHz Operation temperature : -40 ~125 Power supply voltage : 1.6~5.5V Standby function : Oscillation stop Output : CMOS Small chip size : 0.70mm 0.75mm Frequency stability to Vdd : Within ±1ppm Duty cycle : Within 50±5% 1. Part number rule IPS 009 B L z A -C3 Series Name for SPXO Optional Product Series code Crystal Frequency Range 14~27, MHz VDD 1.6~5.5V Divide Function 9:1/512 Divide A:1/1024 Divide Pad Layout C3:Cross S12-1/6 S12.103

2 2. Series Applicable crystal : AT Cut 14MHz~27MHz, MHz Output Frequency (KHz) Part Number Divide Min. Max. IPS009 B L 9 -C /512 IPS009 B L 9 A -C IPS009 B L A A -C /1024 Pad Layout Cross Vdd (V) 1.62 ~ 5.5 Remarks Low Power Consumption 3. Absolute Maximum Ratings Vss=0V, Ta=25 ±2 Parameter Symbol Condition Ratings Min Max Unit Supply Voltage VDD VSS V Input Voltage VIN All Input Pin VSS-0.5 VDD+0.5 V Output Voltage VOUT VSS-0.5 VDD+0.5 V Input Current IIN Pin 50 μa Output Current IOUT 25 ma Junction Temperature Tj Storage Temperature Tstg Recommended Operating Condition V SS =0V, Ta=- 40 ~+125 Supply Voltage Parameter Symbol Condition Min Typ Max Unit Note -40~ V VDD H Input Voltage VIH VDD 0.7 V L Input Voltage VIL VDD 0.3 V Input Voltage VIN VSS VDD V Output IPS009BL9 30 Load IPS009BL9A CL CMOS pf 15 Capacitance Ambient Temperature Topt This IC has enough immunity against ESD and Latch-up, but handle with care. OUT S12-2/6 S12.103

3 5. Electrical Specification Unless otherwise stated, VDD=1.6V~5.5V, VSS=0V, Ta=-40~125 Parameter Symbol Condition Specification Min Typ Max 125 Unit Out put Leak current Iz =0V, X1=VDD, Vss, Vout=Vss~VDD μa H input voltage VIH pad 0.7VDD V L input voltage VIL pad 0.3VDD V H input current IIH pad, VIH=VDD L input current IIL pad, VIL=0V μa Oscillation Disable Time Tplz OUT pad 0.1 μs Oscillation Enable Time Tpzl OUT pad 2 ms Oscillation start up time Tstart VDD>1.6V 2 ms IPS009BL9 OUT pad, IOH=-1.0mA 0.9VDD H output VOH voltage IPS009BL9A OUT pad, IOH=-0.4mA 0.9VDD L output voltage Current consumption IPS009BL9 Current consumption IPS009BL9A Current consumption Output Duty Ratio Rise/Fall time IPS009BL9 IPS009BL9A IPS009BL9 OUT pad, IOL=1.0mA 0.1VDD IPS009BL9A VOL OUT pad, IOL=0.4mA 0.1VDD VDD-0.3V, fxtal=16.777mhz CL=30pF, VDD=1.8V IDD CL=15pF, VDD=3.63V CL=30pF, VDD=3.63V CL=15pF, VDD=5.5V CL=30pF, VDD=5.5V Current consumption at oscillation disable Frequency VDD deviation No Load, VDD-0.3V, fxtal=16.777mhz VDD=3.63V IDD VDD=5.5V No Load, VDD-0.3V, fxtal=27mhz μa VDD=3.63V VDD=5.5V No Load, VDD-0.3V, fxtal=33.554mhz IDD VDD=3.63V μa VDD=5.5V IDDD CL=15pF, VDD=3.3V, 0.3V μa Fvst VDD=3.3±10% ±1 ppm Duty CL=0pF, 15pF, 25pF % 10~90%VDD CL=15pF, VDD=2.5V~5.5V Tr/Tf CL=30pF, VDD=2.5V~5.5V CL=15pF, VDD=1.62V~2.5V CL=30pF, VDD=1.62V~2.5V CL=15pF, VDD=2.5V~5.5V CL=15pF, VDD=1.62V~2.5V V μa ns S12-3/6 S12.103

4 T WH T WL V DD 0.9 V OH V DD 0.5 V DD 0.1 V OL Tr Tf Duty= T WH T WH +T WL 100% Fig. 5-1 Output wave form (Duty, Tr, Tf, VOH, VOL) VIH VIL Tplz Tpzl 1.2V GND Tstart Oscillation Out High-Z Oscillation Out VIH : Threshold voltage for Oscillation Start VIL : Threshold voltage for Oscillation Stop Fig. 5-2 Input output signal timing S12-4/6 S12.103

5 6. Circuit Parameters of Oscillator (Reference Data for Circuit Design) Ta=25 Parameter Symbol Condition Min Typ Max Unit Equivalent series (Loading) VDD=3.3V, CLxtal Capacitance fxtal=16mhz 3.3 pf IPS009BL9 VDD=3.3V, Ta=25 15 Drive Level IPS009BL9A DL fxtal=16mhz μw 1.7 Feedback Resistor Rf 300 KΩ IPS009BL9 600 Driving Resistor IPS009BL9A Rd Ω 1000 Cg 6.0 pf Oscillation IPS009BL9 8.0 Capacitor IPS009BL9A Cd 2.0 pf 2.0 *The above values are the design values and are not guaranteed by test. VDD R f Voltage Regulator Vreg Level Shifter Divider 9 stage Output Buffer OUT R d X1 X2 Cg Cd Fig. 6 Block Diagram S12-5/6 S12.103

6 7. Pad Layout 0.7mm VDD Die Size:0.70mm 0.75mm Pad Size:80um Thickness:150±20um IC Backside:Gnd or Open X1 X2 y VSS x OUT 0.75mm Pad Name Function Location (μm) x y VDD (+)Power Supply OUT(Q) Frequency Output VSS (-)Ground X2 Crystal Drive X1 Crystal Feedback Oscillation stop, "L": High-Impedance Chip Center 0 0 Scribe line center Fig. 7 Pad Layout of IPS009L9, BL9A and BLAA (Cross Type ) Rex IC VSS Package IMPORTANT Notice for function * Rex should be over 10MΩ in case of = Open usage. * Oscillation will not be activated when = Open after = Low if Rex is below 10MΩ. * There is no such issue in case of = VDD usage. Rex : External resistance value between and VSS of package. S12-6/6 S12.103