CARDINAL COMPONENTS. Operating Conditions: Description Min Max Unit

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1 Standard Package Options Series CPP Part Numbering Example: CPP C 1 L Z - A5 B6 - XXXXXX TS CPP C 1 L Z A5 SERIES CPP OUTPUT C = CMOS T = TTL Specifications: PACKAGE STYLE 1 = Full Size 4 = Half Size 5 = 32X5 Ceramic 7 = 5X7 Ceramic 8 = PLASTIC SMD 8B = PLASTIC SMD VOLTAGE Blank = 5V L = 33 V ADDED FEATURES OPERATING TEMP Blank = Bulk Blank = 0 C +70 C T = Tube A5 = -20 C +70 C Z = Tape and Reel A7 = -40 C +85 C B6 STABILITY B6 = ±100 ppm BP = ±50 ppm BR = +25 ppm XXXXXX TS FREQUENCY TRI-STATE 1000~ TS = Tri-State MHz PD=PowerDwn Description Min Typ Max Unit Frequency Range: MHz Programmable to Any Discrete Frequency Available Stability Options: ppm ppm ppm Programmable Supply Voltage: (1 133 MHz) V (1 100 MHz) V Operating Temperature C Range Options: C C Storage Temperature: C Aging (PPM/Year) ±5 Ta=25C, Vdd=5/33V Programmable Output Level: TTL/CMOS Packaging: Tape and Reel (1K per Reel) Tube Operating Conditions: Description Min Max Unit Vdd Supply Voltage V CTTL Max Capacitive Load on outputs for TTL levels 45V 55V Vdd < 40 MHZ 50 pf 45V 55V Vdd > MHZ 25 pf CCMOS Max Capacitive Load on outputs for CMOS levels 45V 55V Vdd, < 66 MHz 50 pf 45V 55V Vdd, > MHz 25 pf 30V 36V Vdd, < 40 MHz 30 pf 30V 36V Vdd, > MHz 15 pf cardinal@cardinalxtalcom 1

2 Series CPP Electrical Characteristics Description TEST CONDITIONS Min Typ Max Unit Input Characteristics (Pin 1): VIL, Low Level Input Voltage 45 55V Vdd 08 V TO DISABLE OUTPUT 30 36V Vdd 02Vdd V VIH, High Level Input Voltage 45 55V Vdd 20 V TO ENABLE OUTPUT OR NO CONNECT 30 36V Vdd 07Vdd V IIL, Input Low Current VIN = 0V 10 µa IIH, Input High Current VIN =Vdd 5 µa Output Characteristics: VOL, Low Level Output Voltage 45V 55V Vdd, 16 ma IOL 04 V 30V 36V Vdd, 8 ma IOL 04 V VOHTTL, 45V 55V Vdd, -16 ma IOL 24 V High-level Output Voltage TTL VOHCMOS, 45V 55V Vdd, -16 ma IOL Vdd-04 V High-level CMOS Voltage 30V 36V Vdd, -8 ma IOL Vdd-04 V Power Supply Current: Vdd, OUTPUT FREQ < 133 MHz 45 ma (unloaded) Vdd, OUTPUT FREQ < 100 MHz 25 ma Standby Current: µa Input Pull-Up Resistor Vdd, VIN = 0V MΩ Vdd, VIN = 07V KΩ Tri-State Leakage Current 50 Vdd 20 µa Output Enable Mode: Power Down Mode: Output is Tri-Stated Output is Tri-Stated cardinal@cardinalxtalcom 2

3 Series CPP Output Clock Switching Characteristics Description TEST CONDITIONS Min Typ Max Unit Duty Cycle: 14 V < 50 MHz, CL = 50 pf % Vdd MHz, CL = 15 pf % MHz, CL = 25 pf % MHz, CL = 15 pf % Duty Cycle: < 66 MHz, CL < 25 pf % Vdd/ MHz, CL < 25 pf % Vdd MHz, CL < 15 pf % Vdd < 40 MHz, CL < 30 pf % MHz, CL < 15 pf % Output Clock Rise/Fall 08V 20V, Vdd, CL = ns 08V 20V, Vdd, CL = ns 08V 20V, Vdd, CL = ns 02 08Vdd, Vdd, CL = ns 02 08Vdd, Vdd, CL = ns 02 08Vdd, Vdd, CL = ns Start Up Time From power on 2 ms Power Down Delay Time Synchronous PWR_DWN pin LOW to output Hi-Z T/2 T+10 ns Asynchronous ns Output Disable Time Synchronous OE pin LOW to output Hi-Z T/2 T+10 ns Asynchronous T = Frequency oscillator period ns Output Enable Time 100 ns Period Jitter: Σ < MHz ps > 33000, MHz ps Peak to Peak * < MHz ps > MHz ps * Jitter tested at > 1,000,000 samples, exceeding JEDEC std JESD65 cardinal@cardinalxtalcom 3

4 CARDINAL COMPONENTS Note: Bypass Vdd to GND with a 001 µf capacitor Style 1 Full Size 14 Pin Dip Style 4 Half Size 8 Pin Dip 7 GND 8 OUTPUT 1 4 GND 5 OUTPUT 8 Vdd Style 7 5x7 Ceramic SMD Style 8 Plastic SMD cardinal@cardinalxtalcom 4

5 CARDINAL COMPONENTS Note: Bypass Vdd to GND with a 001 µf capacitor Style 8B Plastic SMD Style 5 32x5 Ceramic SMD 1 OE cardinal@cardinalxtalcom 5