500MHz TTL/CMOS Potato Chip
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- Frederick Bruce
- 5 years ago
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1 FEATURES:. Patent pending technology. Max input frequency > 1GHz. Operating frequency up to 500MHz with 2pf load. Operating frequency up to 450MHz with 5pf load. Operating frequency up to 300MHz with 15pf load. Operating frequency up to 150MHz with 50pf load. Very low output pin to pin skew < 200ps. Very low pulse skew < 100ps. VCC = 1.65V to 3.6V. Propagation delay < 2.5ns max with 15pf load. Low input capacitance: 3pf typical. 1:7 fanout. Available in 16pin 150mil wide QSOP package. Available in 16pin 173mil wide TSSOP package Pin Configuration DESCRIPTION: Potato Semiconductor s is designed for world top performance using submicron CMOS technology to achieve 500MHz TTL output frequency with less than 100ps output pulse skew. is a 3.3V 1 high speed comparator inputs to 7 TTL output buffered driver to achieve higher than 500MHz output frequency. Typical applications are HSTL, PECL, LVDS to TTL translator, crystal or ring oscillator, clock and signal distribution. Logic Block Diagram Pin Description Pin Name IN+, IN- O1 to O7 Description Inputs Outputs 1
2 Maximum Ratings Description Max Unit Storage Temperature -65 to 150 C Operation Temperature -40 to 85 C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to Vcc+0.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Test Conditions Min Typ Max Unit VOH Output High voltage Vcc=3V Vin=VIH or VIL, IOH= -12mA V VOL Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) V IIH Input High current Vcc = 3.6V and Vin = 3.6V ua IIL Input Low current Vcc = 3.6V and Vin = 0V ua VIK Clamp diode voltage Vcc = Min. And IIN = -18mA V 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 25 C ambient. 3. This parameter is guaranteed but not tested. 4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 5. VoH = Vcc 0.6V at rated current 2
3 Power Supply Characteristics Symbol Description Test Conditions (1) Min Typ Max Unit IccQ Quiescent Power Supply Current Vcc=Max, Vin=Vcc or GND ua Icc Power Supply Current per Input High Vcc=Max, Vin= Vcc-0.6V ua 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 25 C ambient. 3. This parameter is guaranteed but not tested. 4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 5. VoH = Vcc 0.6V at rated current Capacitance Parameters (1) Description Test Conditions Typ Max Unit Cin Input Capacitance Vin = 0V 3 4 pf Cout Output Capacitance Vout = 0V - 6 pf 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) Max Unit tplh Propagation Delay A to Bn CL = 15pF 2.5 ns tphl Propagation Delay A to Bn CL = 15pF 2.5 ns tr/tf Rise/Fall Time 0.8V 2.0V 1 ns tsk(p) Pulse Skew (Same Package) CL = 15pF,V+ = 125MHz, V- = 1.5v 0.2 ns tsk(o) Output Pin to Pin Skew (Same Package) CL = 15pF,V+ = 125MHz, V- = 1.5v 0.1 ns tsk(pp) Output Skew (Different Package) CL = 15pF,V+ = 125MHz, V- = 1.5v 0.4 ns fmax Input Frequency CL = 50pF 150 MHz fmax Input Frequency CL =15pF 300 MHz fmax Input Frequency CL = 5pF 450 MHz fmax Input Frequency CL = 2pF 500 MHz 1. See test circuits and waveforms. 2. tplh, tphl, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3
4 Test Waveforms Test Circuit 50Ω 50Ω 4
5 Packaging Mechanical Drawing: 16 pin QSOP Packaging Mechanical Drawing: 16 pin TSSOP 5
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3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE IDT23S05 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
3.3V ZERO DELAY CLOCK MULTIPLIER
3.3V ZERO DELAY CLOCK MULTIPLIER FEATURES: Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 1 operating frequency Distributes one clock input to two banks of four outputs Separate
PI3C3126. Description. Features. 14-Pin Configuration. Applications. Block Diagram. 16-Pin Configuration. Truth Table (1) Pin Description.
2./3.3, High Bandwidth, Hot Insertion,4-Bit, 2-Port Bus Switch with Individual Enables Features Near-Zero propagation delay -ohm switches connect inputs to outputs High Bandwidth (>400 MHz) 2./3.3 Supply
QUICKSWITCH BASICS AND APPLICATIONS
QUICKSWITCH GENERAL INFORMATION QUICKSWITCH BASICS AND APPLICATIONS INTRODUCTION The QuickSwitch family of FET switches was pioneered in 1990 to offer designers products for high-speed bus connection and
Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664
Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664 FEATURES ±15 kv ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 100 ps channel-to-channel
PI6C B. 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram
Features Maximum output frequency: 500MHz 4 pair of differential LPECL outputs Selectable and crystal inputs accepts LCMOS, LTTL input level Ultra low additive phase jitter: < 0.05 ps (typ) (differential
SN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
PI6CL V/1.5V, 200MHz, 1:4 Networking Clock Buffer. Features. Description. Pin Description
Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply
SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS
Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
Description. Pin Description
4-bit LVTTL to GTL transceiver Features Operates as a 4-bit GTL /GTL/GTL+ sampling receiver or as a LVTTL to GTL /GTL/GTL+ driver 2.3 V to 3.6 V operation with 5 V tolerant LVTTL input GTL input and output
ICS Low Skew PCI / PCI-X Buffer. General Description. Block Diagram. Pin Configuration. Pin Descriptions OE CLK0
Low Skew PCI / PCI-X Buffer General Description The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications
3.3V ZERO DELAY CLOCK BUFFER
3.3V ZERO DELAY CLOCK BUFFER IDT2309 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 1 operating frequency Distributes one clock input to one bank of five and one bankd of four outputs Separate output
SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram
Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation
PI3L V Quad, 2:1 Mux/DeMux Fast Ethernet LAN Switch w/ Single Enable. Description. Features. Applications. Pin Configuration.
Features R ON is 4Ω typical Low crosstalk: 27dB @ 250 MHz Near-Zero propagation delay: 250ps Switching speed: 9ns Channel On capacitance: 9pF (typical) Operating Range: +3.0V to +3.6V >2kV ESD protection
SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
PI3DBS V High Speed 2 : 4 Differential Mux/Demux
3.3V High Speed 2 : 4 Differential Mux/Demux Features ÎÎ2:4 Differential Multiplexer/Demultiplexer ÎÎBidirectional Operation ÎÎCan be used in à à Single :4 Configuration à à Dual :2 Configuration à à Fan
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
PI5C16861 PI5C (25Ω) 20-Bit, 2-Port Bus Switch
PI5C8 PI5C28 (25Ω) Features Near-Zero propagation delay 5Ω or 25Ω switches connect inputs to outputs Direct bus connection when switches are ON 32X384 function with flow through pinout make board layout