LOW-VOLTAGE QUADRUPLE BUS SWITCH 11 4B

Transcription

1 LOW-VOLTAGE QUADRUPLE BUS ITCH IDT7CBTLV6 FEATURES: Pin-out compatible with standard '6 Logic products Ω A/B bi-directional switch Isolation under power-off conditions Over-voltage tolerant Latch-up performance exceeds 00mA =.V -.6V, Normal Range ESD > 00 per MIL-STD-88, Method 0; > 0 using machine model (C = 00pF, R = 0) Output enable, active high Available in QSOP and TSSOP packages APPLICATIONS:.V High Speed Bus Switching and Bus Isolation DESCRIPTION: The CBTLV6 features four independent switches. Each switch is enabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTIONAL BLOCK DIAGRAM SIMPLIFIED SCHEMATIC, EACH ITCH A B OE A 6 B A B OE A 9 8 B OE 0 A B OE OE. Pin numbers shown apply to the -pin TSSOP package. The IDT logo is a registered trademark of Integrated Device Technology, Inc. JULY Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-70/6

2 PIN CONFIGURATION OE A OE B A OE B A 0 OE B 6 9 A 7 8 B NC OE A B OE A B OE A B OE A B NC TSSOP TOP VIEW QSOP TOP VIEW ABSOLUTE MAXIMUM RATINGS () Symbol Description Max Unit SupplyVoltage Range 0. to +.6 V VI Input Voltage Range 0. to +.6 V Continuous Channel Current 8 ma IIK Input Clamp Current, VI/O < 0 0 ma TSTG Storage Temperature 6 to +0 C. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTION TABLE () Input OE H L. H = HIGH Voltage Level L = LOW Voltage Level Inputs/Outputs A Port = B Port Disconnect OPERATING CHARACTERISTICS, TA = C () Symbol Parameter Test Conditions Min. Max. Unit Supply Voltage..6 V High-Level Control Input Voltage =.V to.7v.7 V =.7V to.6v VIL Low-Level Control Input Voltage =.V to.7v 0.7 V =.7V to.6v 0.8 TA Operating Free-Air Temperature 0 8 C. All unused control inputs of the device must be held at or to ensure proper device operation.

3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Conditions: TA = 0 C to +8 C Symbol Parameter Test Conditions Min. Typ. () Max. Unit VIK Control Inputs, Data Inputs = V, II = 8mA. V II Control Inputs =.6V, VI = or ± µa IOZ Data I/O =.6V, VO = 0 or.6v, switch disabled µ A IOFF = 0, VI or VO = 0 to.6v 0 µ A ICC =.6V, IO = 0, VI = or 0 µ A ICC () Control Inputs =.6V, one input at V, other inputs at or 00 µ A CI Control Inputs VI = V or 0 pf CIO(OFF) VO = V or 0, OE = 6 pf =.V VI = 0 IO = 6mA 8 Typ. at =.V IO = ma 8 RON () VI =.7V IO = ma 7 0 Ω VI = 0 IO = 6mA 7 = V IO = ma 7 VI =.V IO = ma 0 NOTES:. Typical values are at =.V, + C ambient.. The increase in supply current is attributable to each current that is at the specified voltage level rather than or.. This is measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B ) terminals. ITCHING CHARACTERISTICS =.V ± 0.V =.V ± 0.V Symbol Parameter Min. Max. Min. Max. Unit tpd () Propagation Delay ns A to B or B to A ten Output Enable Time.. ns OE to A or B tdis Output Disable Time.7.8 ns OE to A or B. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance driven by an ideal voltage source (zero output impedance).

4 TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol () =.V±0.V () =.V±0.V Unit VLOAD 6 x Vcc V Vcc V. Vcc / V VLZ 00 0 mv VHZ 00 0 mv CL 0 0 pf (, ) Pulse Generator VIN RT D.U.T. VOUT CL Test Circuits for All Outputs 00Ω 00Ω DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES:. Pulse Generator for All Pulses: Rate 0MHz; tf.ns; tr.ns.. Pulse Generator for All Pulses: Rate 0MHz; tf ns; tr.ns. VLOAD Open SAME PHASE INPUT TRANSITION OPPOSITE PHASE INPUT TRANSITION CONTROL INPUT tplh tplh ITCH NORMALLY CLOSED LOW tpzh NORMALLY HIGH ENABLE ITCH OPEN Propagation Delay tpzl VLOAD/ tphz tphl tphl Enable and Disable Times DISABLE tplz VOH VOL VLOAD/ VOL + VLZ VOL VOH VOH -VHZ ITCH POSITION Test tplz/tpzl tphz/tpzh tpd Switch VLOAD Open

5 ORDERING INFORMATION IDT XX CBTLV XXXX X Temp. Range Device Type Package PG PGG Q QG Thin Shrink Small Outline Package TSSOP - Green Quarter Small Outline Package QSOP - Green 6 Low-Voltage Quadruple Bus Switch 7-0 C to +8 C DATASHEET DOCUMENT HISTORY 07//008 pg.. CORPORATE HEADQUARTERS for SALES: for Tech Support: 60 Silver Creek Valley Road or logichelp@idt.com San Jose, CA 98 fax: