FAST CMOS 1-TO-10 CLOCK DRIVER

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1 Integrated Device Technology, Inc. FAST CMOS 1-TO-10 CLOCK DRIVER IDT54/74FCT807BT/CT FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 250ps (max.) Very low duty cycle distortion < 350ps (max.) High speed: propagation delay < 2.5ns (max.) 100MHz operation TTL compatible inputs and outputs TTL level output voltage swings 1:10 fanout Output rise and fall time < 1.5ns (max.) Low input capacitance: 4.5pF typical High Drive: -32mA IOH, 48mA IOL ESD > 200 per MIL STD-883, Method 3015; FUNCTIONAL BLOCK DIAGRAM > 20 using machine model (C = 200pF, R = 0) Available in DIP, SOIC, SSOP, QSOP, Cerpack and LCC packages Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT54/74FCT807BT/CT clock driver is built using advanced dual metal CMOS technology. This low skew clock driver features 1:10 fanout, providing minimal loading on the preceding drivers. The IDT54/74FCT807BT/CT offers low capacitance inputs with hysteresis for improved noise margins. TTL level outputs and multiple power and grounds reduce noise. The device also features -32/48mA drive capability for driving low impedance traces. P CONFIGURATIONS 1 20 O O10 O2 O3 O4 O1 O2 O P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E O9 O8 O7 O5 O6 O O6 O5 O7 O8 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW 3017 drw 02 O9 DEX O1 O10 O O drw 01 O L O8 O O7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. OCTOBER Integrated Device Technology, Inc. 9.3 DSC-4242/3 1 O4 O5 O6 LCC TOP VIEW 3017 drw 03

2 P DESCRIPTION Pin Names Ox Input Outputs Description ABSOLUTE MAXIMUM RATGS (1) 3017 tbl 01 Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage 0.5 to to +7.0 V with Respect to VTERM (3) Terminal Voltage 0.5 to 0.5 to V with Respect to TA Operating 0 to to +125 C Temperature TBIAS Temperature 55 to to +135 C Under Bias TSTG Storage Temperature 55 to to +150 C IOUT DC Output 60 to to +120 ma Current 3017 lnk Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed by +0.5V unless otherwise noted. 2. Input and terminals. 3. Output and I/O terminals. CAPACITANCE (TA = +25 C, f = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit C Input V = pf Capacitance COUT Output VOUT = pf Capacitance NOTE: 1. This parameter is measured at characterization but not tested lnk

3 DC ELECTRICAL CHARACTERISTICS OVER OPERATG RANGE Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0 C to +70 C, = 5. ± 5%; Military: TA = 55 C to +125 C, = 5. ± 10% Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V II H Input HIGH Current (5) = Max. VI = 2.7V ±1 µa II L Input LOW Current (5) = Max. VI = 0.5V ±1 µa IOZH High Impedance Output Current = Max. VO = 2.7V ±1 µa IOZL (3-State Output pins) (5) VO = 0.5V ±1 µa II Input HIGH Current (5) = Max., VI = (Max.) ±1 µa VIK Clamp Diode Voltage = Min., I= 18mA V IOS Short Circuit Current = Max. (3), VO = ma Output HIGH Voltage = Min. IOH = 12mA MIL V V = VIH or VIL IOH = 15mA COM'L. IOH = 24mA MIL IOH = 32mA COM'L. (4) Output LOW Voltage = Min. V = VIH or VIL IOL = 32mA MIL. IOL = 48mA COM'L V IOFF Input/Output Power Off Leakage (5) =, V or VO 4.5V ±1 µa VH Input Hysteresis for all inputs 150 mv ICCL ICCH Quiescent Power Supply Current = Max., V = or µa ICCZ 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5., +25 C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ± 5µA at TA = 55 C. POWER SUPPLY CHARACTERISTICS 3017 lnk 04 Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit ICC Quiescent Power Supply Current TTL Inputs HIGH = Max. V = 3.4V ICCD Dynamic Power Supply Current (3) = Max. Input toggling 50% Duty Cycle Outputs Open IC Total Power Supply Current (5) = Max. Input toggling 50% Duty Cycle Outputs Open fi = 50MHz V = V = V = V = V = 3.4V V = ma ma/ MHz (4) ma (4) 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at = 5., +25 C ambient. 3. Per TTL driven input; (V = 3.4V); all other inputs at or. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (V = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fi= Input Frequency All currents are in milliamps and all frequencies are in megahertz tbl

4 SWITCHG CHARACTERISTICS OVER OPERATG RANGE (3,4) IDT54/74FCT807BT IDT54/74FCT807CT Com'l. Mil. Com'l. Mil. Symbol Parameter Conditions (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay 50Ω to /2, CL = 10pF ns tr Output Rise Time (See figure 1) ns tf Output Fall Time or 50Ω ac ns tsk(p) IDT54/74FCT807BT IDT54/74FCT807CT Com'l. Mil. Com'l. Mil. Symbol Parameter Conditions (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 30pF ns f 67MHz tr Output Rise Time (See figure 3) ns tf Output Fall Time ns tsk(p) Output skew: skew between outputs of same package (same transition) skew: skew between opposite transitions of same output ( - tplh ) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output skew: skew between outputs of same package (same transition) skew: skew between opposite transitions of same output ( - tplh ) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade termination, CL = 10pF (See figure 2) f 100MHz Outputs connected in groups of two ns ns ns 3017 tbl ns ns ns IDT54/74FCT807BT IDT54/74FCT807CT Com'l. Mil. Com'l. Mil tbl 07 Symbol Parameter Conditions (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 50pF ns f 40MHz tr Output Rise Time (See figure 4) ns tf Output Fall Time ns tsk(p) Output skew: skew between outputs of same package (same transition) skew: skew between opposite transitions of same output ( - tplh ) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade ns ns ns 3017 tbl See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tplh,, are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to, operating temperature and process parameters. These propagation delay limits do not imply skew

5 TEST CIRCUITS 50Ω TO /2, CL = 10pF 50Ω AC TERMATION, CL = 10pF 100Ω V 100Ω 10pF V VOUT 50Ω 220pF 10pF Figure drw drw 05 The capacitor value for ac termination is determined by the operating frequency. For very low frequencies a higher capacitor value should be selected. Figure 2. CL = 30pF CIRCUIT CL = 50pF CIRCUIT V 30pF V 50pF CL C L 3017 drw drw 07 Figure 3. Figure 4. ENABLE AND DISABLE TIME CIRCUIT ENABLE AND DISABLE TIME SWITCH POSITION V 50pF C L 500Ω 500Ω 7. Test Disable LOW Enable LOW Disable HIGH Enable HIGH Switch Closed Open DEFITIONS: 3017 lnk 09 CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the drw 08 Figure

6 TEST WAVEFORMS PACKAGE DELAY SKEW- tplh tr tf V 1 2 tplh1 tplh drw 09 = tplh2 - tplh1 or drw 10 PULSE SKEW - tsk(p) PACKAGE SKEW - tplh tsk(p) = - tplh PACKAGE 1 PACKAGE 2 tplh1 tplh2 1 2 ENABLE AND DISABLE TIMES 3017 drw 11 = tplh2 - tplh1 or 2-1 Package 1 and Package 2 are same device type and speed grade 3017 drw 12 CONTROL NORMALLY LOW NORMALLY HIGH ENABLE t PZL SWITCH CLOSED t PZH SWITCH OPEN 3.5V t PHZ DISABLE t PLZ V 3017 drw Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. for All s: f 1.0MHz; tf 2.5ns; tr 2.5ns 9.3 6

7 ORDERG FORMATION IDT XX Temp. Range FCT XXXX Device Type X Package X Process Blank B P D SO L E PY Q 807BT 807CT Commercial MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Shrink Small Outline IC Quarter-size Small Outline IC 1-to-10 Clock Driver C to +125 C 0 C to +70 C 3017 drw

3.3V CMOS 1-TO-10 CLOCK DRIVER

3.3V CMOS 1-TO-10 CLOCK DRIVER 3. CMOS 1-TO-10 CLOCK DRIVER 3. CMOS 1-TO-10 CLOCK DRIVER IDT74/A FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 350ps (max.) Very low duty cycle distortion < 350ps (max.) High speed: propagation