ICS Low Skew PCI / PCI-X Buffer. General Description. Block Diagram. Pin Configuration. Pin Descriptions OE CLK0
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1 Low Skew PCI / PCI-X Buffer General Description The ICS is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications operating at speeds from 0 to 140 MHz. The ICS is characterized for operation from -40 C to 85 C for automotive and industrial applications. Features Frequency range MHz (3.3V) Less than 200 ps Jitter between outputs Skew controlled outputs < 100 ps Distribute one clock input to one bank of four outputs 3.3V ±10% operation Available in 8 pin TSSOP, and SOIC packages. Block Diagram Pin Configuration OE LOGIC CONTROL CLK0 CLK1 CLK_IN OE CLK0 GND ICS CLK3 CLK2 VDD CLK1 CLK_IN 8 pin TSSOP & SOIC CLK2 Functionality Table CLK3 CLK_IN INPUTS OUTPUTS O E CLK(3:0) 0 0 Tristate Tristate Pin Descriptions PIN NUMBER PIN NAME 1 CLK_IN 2 OE TYPE I N Input reference frequency. IN Output enable. When DESCRIPTION OE is low, it tristates the clock outputs 3 CLK0 4 GND 5 CLK1 6 VDD 7 CLK2 8 CLK3 OUT PWR OUT PWR OUT OUT Buffered clock output Ground Buffered clock output Power supply for 3.3V Buffered clock output Buffered clock output
2 Absolute Maximum Ratings Supply voltage range V DD V to 4.3 V Input voltage range V I (see notes 1 & 2) V to V DD + 0.5V Output voltage range VO (see notes 1 & 2) V to VDD + 0.5V Input clamp current IIK (VI< 0 or VI >VDD) ±50 ma Output clamp current I OK (V O < 0 or V O ) ±50 ma Continuous total output current, I O (V O = 0 to V DD ) ±50 ma Package thermal impedance Ø JA (see note 3): PW package230.5 C/W Storage temperature rante, T stg C to 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions Min Nom Max Unit Supply voltage, VDD V High-level input voltage, VIH 0. 7 X V DD V Low-level input voltage, VIL 0. 3 X V DD V Input voltage, VI 0 V DD V High-level output current, IOH -24 ma Low-level output current, IOL 24 ma Operating free-air temperature, TA C Timing requirements over recommended ranges of supply voltage and operating free-air temperature Clock Min Nom frequency fclk MHz Max Unit 2
3 Electrical Characteristics at 3.3V T A = -40 to 85 C; Supply Voltage V DD = 3.3 V +/-10% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input voltage V IK V DD = 3.3V, I I = -18 ma -1.2 V V DD = min to max, I OH = -1 ma V DD High-level Output Voltage V OH V DD = 3V, I OH = -24 ma V V DD = 3V, I OH = 12 ma V DD = min to max, I OH = 1 ma Low-level Output Voltage V OL V DD = 3V, I OH = 24 ma V V DD = 3V, I OH = 12 ma High-level Input Current I OH V DD = 3V, V O = 1V V DD = 3.3V, V O = 1.65V -54 ma Low-level Input Current I OL V DD = 3V, V O = 2V V DD = 3.3V, V O = 1.65V 57 ma Input Current I I V = V O or V DD -5 5 ma Dynamic Supply Current I DD Unloaded outputs at MHz ma Input Capacitance 1 C I V DD = 3.3V, V I = 0V or 3.3V 3 pf Output Capacitance 1 C O V DD = 3.3V, V I = 0V or 3.3V 3.2 pf 1. Guaranteed by design, not 100% tested in production. Switching Characteristics at 3.3V T A = -40 to 0 85 C; Supply Voltage V DD = 3.3 V +/-10% (For loading, see figures 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-to-low Propagation Delay 1 t PLH V O = V DD / ns Low-to-high Propagation Delay 1 t PHL V O = V DD / ns Output Skew Window 1 T sk (o) V O = V DD / ps Pulse Skew = t PLH - t PHL 1 T sk (p) V O = V DD /2 300 ps Process Skew 1 T sk (pr) V O = V DD /2 500 ps CLKIN High Time 1 CLKIN Low Time 1 T high T low 66 MHz 66 MHz MHz 140 MHz 3 3 ns ns Output Rise Slew Rate 1 T r 0.3 to 0.6 V DD V/ns Output Rise Slew Rate 1 T f 0.6 to 0.3 V DD V/ns 1. Guaranteed by design, not 100% tested in production. 3
4 Parameter Measurement Information V DD 140 CLK n 10 pf 140 Figure 1. Test Load Circuit V DD 50% V DD CLKIN 0V t PLH T PHL 0.6 V DD 0.6 V DD 50% VDD V OH CLK0-CLK3 50% V DD 0.2 VDD 0.2 V DD V OL t R t f Figure 2. Voltage Thresholds for Propagation Delay (t pd) Measurements 50% V DD Any CLK 50% V DD Any CLK T sk(0) Figure 3. Output Skew Paramameter Parameter Value Unit tcyc V IH(Min) 0.5 V DD V t high V IL(Max) 0.35 V DD V V test 0.4 V DD V V IH(Min) V test 0.6 V DD t low V IL(Max) Figure 4. Clock Waveform 0.2 V DD 0.4 VDD Peak to Peak (Minimum) Note: All parameters in Figure 4 are according to PCI-X 1.0 specifications. 4
5 ICS9112AG-27 SUPPLY CURRENT vs. FREQUENCY V DD = 3.63 V, T A = 85 o C IDD (ma) Frequency (MHz) ICS9112AG-27 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT V DD = 3.3V, T A = 25 o C VOH - High-Level Output Current (ma) IOH - High-Level Output Current (ma) 5
6 3.5 ICS9112AG-27 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT V DD = 3.3V, T A = 25 o C VOL - Low-Level Output Current (ma) IOL - Low-Level Output Current (ma) 6
7 INDEX AREA A2 N 1 2 D E1 A E c L 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D E SEE VARIATIONS 6.40 BASIC SEE VARIATIONS BASIC E e 0.65 BASIC BASIC L N SEE VARIATIONS SEE VARIATIONS aaa e -Cb A1 SEATING PLANE C aaa VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MO mm. Body, 0.65 mm. pitch TSSOP (173 mil) ( Inch) Ordering Information 9112AG-27LFT Example: XXXX A G -YYLF T Designation for tape and reel packaging Annealed Lead Free (Optional) Die revision code Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 7
8 INDEX AREA N 1 2 D E A1 H h x 45 A C L 150 mil (Narrow Body) SOIC In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A B C D SEE VARIATIONS SEE VARIATIONS E e 1.27 BASIC BASIC H h L N SEE VARIATIONS SEE VARIATIONS e B 150 mil (Narrow Body) SOIC SEATING PLANE.10 (.004) VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MS Ordering Information 9112AM-27LFT Example: XXXX A M -YYLF T Designation for tape and reel packaging Annealed Lead Free (Optional) Die revision code Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type 8
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SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve
ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or
SN54HC04, SN74HC04 HEX INVERTERS
SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
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MM74HC86 Quad 2-Input Exclusive OR Gate
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LOCO PLL CLOCK MULTIPLIER. Features
DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
FSUSB22 Low-Power, 2-Port, High-Speed USB 2.0 (480Mbps) Switch
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FIN V LVDS High Speed Differential Driver/Receiver
April 2001 Revised September 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage
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DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate
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SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
Features VDD 2. 2 Clock Synthesis and Control Circuitry. Clock Buffer/ Crystal Oscillator GND
DATASHEET Description The is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a.5 MHz or 5.00
PO74G139A. Pin Configuration. Logic Block Diagram. Pin Description. 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION:
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 800MHz with 5pf load. Operating frequency up to 350MHz with 15pf load. VCC Operates from 1.65V
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT
MM74HC132 Quad 2-Input NAND Schmitt Trigger
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ICS9214. Rambus TM XDR TM Clock Generator. General Description. Pin Configuration. Block Diagram ICS9214. Integrated Circuit Systems, Inc.
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Parameters Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f MHz
Features Any frequency between 1 MHz and 110 MHz accurate to 6 decimal places Operating temperature from -40 C to +85 C. Refer to MO2018 for -40 C to +85 C option and MO2020 for -55 C to +125 C option
REVISIONS LTR DESCRIPTION DATE APPROVED Thomas M. Hess. Update boilerplate to current MIL-PRF requirements. - PHN
REVISIONS LTR DESCRIPTION DTE PPROVED Update boilerplate to current MIL-PRF-38535 requirements. - PHN 14-06-24 Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME 43218-3990
FIN1532 5V LVDS 4-Bit High Speed Differential Receiver
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DM74ALS169B Synchronous Four-Bit Up/Down Counters
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DM74ALS174 DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
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M74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation