LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

Transcription

1 S599T LOW SKEW TTL PLL CLOCK IVE WITH INTEGATE LOOP FILTE S599T FEATUES: 5V operation Low noise TTL level outputs < 350ps output skew, 0-4 2x output, output, output, /2 output Outputs tri-state and reset while OE/ST low PLL disable feature for low frequency testing Internal loop filter C network Functional equivalent to Motorola MC8895 Positive or negative edge synchronization (PE) Balanced rive Outputs ± 24mA 60MHz maximum frequency (2x output) Available in SOP and PLCC packages ESCIPTION The S599T Clock river uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2x, 0-4, 5, /2. Careful layout and design ensure <350ps skew between the 0-4, and /2 outputs. The S599T includes an internal C filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or C testing. The LOCK output asserts to indicate when phase lock has been achieved. The S599T is designed for use in highperformance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK IAGAM EF_SEL LOCK PE FEEBACK PLL_EN FE_SEL OE/ST SYNC0 SYNC 0 PHASE ETECTO LOOP FILTE VCO 0 /2 0 / x The IT logo is a registered trademark of Integrated evice Technology, Inc. SEPTEMBE Integrated evice Technology, Inc. SC-585/

2 S599T PIN CONFIGUATION OE/ST 5 4 2x x OE/ST 4 25 /2 FEEBACK 5 25 /2 FEEBACK 5 24 EF_SEL 6 24 EF_SEL SYNC SYNC A 8 22 A PE A SYNC FE_SEL LOCK PLL_EN PE A SYNC FE_SEL 0 PLL_EN 2 LOCK SOP TOP VIEW PLCC TOP VIEW ABSOLUTE MAXIMUM ATINGS () Symbol ating Max Unit, A Supply Voltage to Ground 0.5 to +7 V VIN C Input Voltage VIN 0.5 to +7 V Maximum Power SOP 655 mw issipation (TA = 85 C) PLCC 770 TSTG Storage Temperature ange 65 to +50 C CAPACITANCE (TA = +25 C, f =.0MHz, VIN = 0V) SOP PLCC Parameter Typ. Max. Typ. Max. Unit CIN pf NOTE:. Stresses greater than those listed under ABSOLUTE MAXIMUM ATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2

3 S599T PIN ESCIPTION Pin Names I/O escription SYNC0 I eference clock input SYNC I eference clock input EF_SEL I eference clock select. When, selects SYNC. When 0, selects SYNC0. FE_SEL I VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. FEEBACK I PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. 0-4 O Clock outputs 5 O Clock output. Matched in frequency, but inverted with respect to. 2x O Clock output. Matched in phase, but frequency is double the frequency. /2 O Clock output. Matched in phase, but frequency is half the frequency. LOCK O PLL lock indication signal. indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. OE/ST I Output enable/asynchronous reset. esets all output registers. When 0, all outputs are held in a tri-stated condition. When, outputs are enabled. PLL_EN I PLL enable. Enables and disables the PLL. Useful for testing purposes. PE I When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. Power supply for output buffers. A Power supply for phase lock loop and other internal circuitries. Ground supply for output buffers. A Ground supply for phase lock loop and other internal circuitries. OUTPUT FEUENCY SPECIFICATIONS Industrial: TA = 40 C to +85 C, A/ = 5V ± 0% Symbol escription Units FMAX_2X Max Frequency, 2x MHz FMAX_ Max Frequency, 0-4, MHz FMAX_/2 Max Frequency, / MHz FMIN_2X Min Frequency, 2x MHz FMIN_ Min Frequency, 0-4, MHz FMIN_/2 Min Frequency, / MHz 3

4 S599T FEUENCY SELECTION TABLE SYNC (MHz) Output Used for (allowable range) Output Frequency elationships (2) FE_SEL Feedback Min. Max /2 5 Outputs 2X HIGH /2 FMIN_/2 FMAX _/2 SYNC SYNC X 2 SYNC X 2 SYNC X 4 HIGH 0-4 FMIN_ FMAX _ SYNC / 2 SYNC SYNC SYNC X 2 HIGH 5 FMIN_ FMAX _ SYNC / 2 SYNC SYNC SYNC X 2 HIGH 2x FMIN_2X FMAX _2X SYNC / 4 SYNC / 2 SYNC / 2 SYNC LOW /2 FMIN_/2 /2 FMAX _/2 /2 SYNC SYNC X 2 SYNC X 2 SYNC X 4 LOW 0-4 FMIN_ /2 FMAX _ /2 SYNC / 2 SYNC SYNC SYNC X 2 LOW 5 FMIN_ /2 FMAX _ /2 SYNC / 2 SYNC SYNC SYNC X 2 LOW 2x FMIN_2X /2 FMAX _2X /2 SYNC / 4 SYNC / 2 SYNC / 2 SYNC NOTES:. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2X. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FE_SEL only affects VCO frequency and does not affect output frequencies. 2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz. C ELECTICAL CHAACTEISTICS OVE OPEATING ANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40 C to +85 C, A/ = 5V ± 0% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage Level Guaranteed Logic HIGH level 2 V VIL Input LOW Voltage Level Guaranteed Logic LOW level 0.9 V VOH Output HIGH Voltage = Min., IOH = 24mA 2.4 V = Min., IOH = 00µA 3 VOL Output LOW Voltage = Min., IOL = 24mA 0.45 V = Min., IOL = 00µA 0.2 VH Input Hysteresis 00 mv IOZ Output Leakage Current VOUT = or, = Max. 5 µa IIN Input Leakage Current VIN = A or, A = Max. 5 µa IP Input Pull-own Current (PE) A = Max., VIN = A 00 µa POWE SUPPLY CHAACTEISTICS Symbol Parameter Test Conditions Typ. Max. Unit I uiescent Power Supply Current = Max., OE/ST = LOW,.5 ma SYNC = LOW, All outputs unloaded I Power Supply Current per Input HIGH = Max., VIN = 3.4V ma I ynamic Power Supply Current () = Max., CL = 0pF ma/mhz NOTE:. elative to the frequency of outputs. 4

5 S599T INPUT TIMING EUIEMENTS Symbol escription Min. Max. Unit t, tf Maximum input rise and fall times, 0.8V to 2V 3 ns FI Input Clock Frequency, SYNC0, SYNC () 2.5 FMAX_2x MHz tpwc Input clock pulse, HIGH or LOW (2) 2 ns H uty cycle, SYNC0, SYNC (2) % NOTES:. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEBACK and FE_SEL combinations. 2. Where pulse witdh implied by H is less than twpc limit, twpc limit applies SWITCHING CHAACTEISTICS () Symbol Parameter () Min. Max. Unit tsk Output Skew Between ising Edges, 0-4 and /2 (2) 350 ps tskf Output Skew Between Falling Edges, 0-4 and /2 (2) 350 ps tskall Output Skew, All Outputs (2,5) 500 ps tpw Pulse Width, 2x output, >40MHz TCY/2 0.4 TCY/ ns tpw Pulse Width, 0-4, 5, /2 outputs, 80MHz TCY/2 0.4 TCY/ ns tj Cycle-to-Cycle Jitter (4) ns tp SYNC Input to Feedback elay (6) ps tlock SYNC to Phase Lock 0 ms tpzh Output Enable Time, OE/ST LOW to HIGH (3) 0 7 ns tpzl tphz Output Enable Time, OE/ST HIGH to LOW (3) 0 6 ns tplz t, tf Output ise/fall Times, 0.8V 2V ns NOTES:. See Test Loads and Waveforms for test load and termination. Test circuit is used for output enable/disable parameters. Test circuit 2 is used for all other timing parameters. 2. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). 3. Measured in open loop mode PLL_EN = Jitter is characterized with output at 20MHz. See FEUENCY SELECTION TABLE for information on proper FE_SEL level for specified input frequencies. 5. Skew measured at selected synchronization edge. 6. tp measured at device inputs at.5v, output at 80MHz. 5

6 S599T AC TEST LOAS AN WAVEFOMS 300Ω 7.0V 60Ω OUTPUT OUTPUT 30pF 300Ω 68Ω 20pF Test Circuit Test Circuit 2.0ns.0ns t tf 3.0V 2.0V Vth =.5V 0.8V 0V 2.0V.5V tpw 0.8V 0V TTL Test Input Waveform TTL Output Waveform ENABLE ISABLE 3V CONTOL INPUT.5V 0V OUTPUT NOMALLY LOW SWITCH CLOSE tpzl.5v tplz 0.3V 3.5V VOL tpzh tphz OUTPUT NOMALLY HIGH SWITCH OPEN.5V 0.3V VOH 0V Enable and isable Times TEST CICUIT is used for output enable/disable parameters. TEST CICUIT 2 is used for all other timing parameters. 6

7 S599T AC TIMING IAGAM SYNC tp FEEBACK tj tskf 0-4 tsk /2 2x t SKALL 5 NOTES:. AC Timing iagram applies to output connected to FEEBACK and PE =. For PE =, the negative edge of FEEBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at.5v. 7

8 S599T PLL OPEATION The Phase Locked Loop (PLL) circuit included in the S599T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, propagation delay can even be negative! A simplified schematic of the S599T PLL circuit is shown below. SIMPLIFIE IAGAM OF S599T FEEBACK 2x /2 INPUT VCO /2 /2 PHASE ETECTO The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the S599T typically provides within 50ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 8

9 S599T OEING INFOMATION S XXXX evice Type XX Speed X Package X Process Blank Industrial (-40 C to +85 C) J uarter Size Outline Package Plastic Leaded Chip Carrier MHz Max. Frequency 70MHz Max. Frequency 00MHz Max. Frequency 33MHz Max. Frequency 60MHz Max. Frequency 599T Low Skew TTL PLL Clock river with Integrated Loop Filter COPOATE HEAUATES for SALES: for Tech Support: 2975 Stender Way or logichelp@idt.com Santa Clara, CA fax: (408)