8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS

Transcription

1 TECHNICAL ATA IN74AC323 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS The IN74AC323 is identical in pinout to the LS/ALS323, HC/HCT323. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The IN74AC323 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 2 pin package. ue to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode- Select lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs. Outputs irectly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2. to 6. V Low Input Current: 1. μa;.1 25 C High Noise Immunity Characteristic of CMOS evices Outputs Source/Sink 24 ma ORERING INFORMATION IN74AC323N Plastic IN74AC323W SOIC TA = -4 to 85 C for all packages PIN ASSIGNMENT LOGIC IAGRAM PIN 2=VCC PIN 1 = GN 1

2 MAXIMUM RATINGS * Symbol Parameter Value Unit VCC C Supply Voltage (Referenced to GN) -.5 to +7. V VIN C Input Voltage (Referenced to GN) -.5 to VCC +.5 V VOUT C Output Voltage (Referenced to GN) -.5 to VCC +.5 V IIN C Input Current, per Pin ±2 ma IOUT C Output Sink/Source Current, per Pin ±5 ma ICC C Supply Current, VCC and GN Pi ±5 ma P Power issipation in Still Air, Plastic IP+ SOIC Package+ Tstg Storage Temperature -65 to +15 C TL Lead Temperature, 1 mm from Case for 1 Seconds (Plastic IP or SOIC Package) 75 5 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +erating - Plastic IP: - 1 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 26 C RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit VCC C Supply Voltage (Referenced to GN) V VIN, VOUT C Input Voltage, Output Voltage (Referenced to GN) VCC V TJ Junction Temperature (PIP) 14 C TA Operating Temperature, All Package Types C IOH Output Current - High -24 ma IOL Output Current - Low 24 ma tr, tf Input Rise and Fall Time * (except Schmitt Inputs) VCC =3. V VCC = V VCC = V /V * VIN from 3% to 7% VCC This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be cotrained to the range GN (VIN or VOUT) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or VCC). Unused outputs must be left open. 2

3 C ELECTRICAL CHARACTERISTICS(Voltages Referenced to GN) VCC Guaranteed Limits Symbol Parameter Test Conditio V 25 C -4 C to 85 C VIH Minimum High- Level Input Voltage VIL Maximum Low - Level Input Voltage VOH Minimum High- Level Output Voltage VOUT=.1 V or VCC-.1 V 3. VOUT=.1 V or VCC-.1 V 3. IOUT -5 μa Unit V V V * VIN=VIH or VIL IOH=-12 ma IOH=-24 ma IOH=-24 ma VOL Maximum Low- Level Output Voltage IOUT 5 μa V IIN IOZ IOL IOH ICC Maximum Input Leakage Current Maximum Three- State Leakage Current +Minimum ynamic Output Current +Minimum ynamic Output Current Maximum Quiescent Supply Current (per Package) * VIN= VIH or VIL IOL=12 ma IOL=24 ma IOL=24 ma VIN=VCC or GN ±.1 ±1. μa VIN (OE)= VIH or VIL VIN =VCC or GN VOUT =VCC or GN ±.6 ±6. μa VOL=1.65 V Max 75 ma VOH=3.85 V Min -75 ma VIN=VCC or GN 8. 8 μa * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2. ms, one output loaded at a time. Note: IIN and 3. V are guaranteed to be less than or equal to the respective V VCC 3

4 AC ELECTRICAL CHARACTERISTICS(CL=5pF,Input tr=tf=3. ) VCC * Guaranteed Limits Symbol Parameter V 25 C -4 C to 85 C fmax Maximum Clock Frequency (Figure 1) tplh tphl tplh tphl tpzh tpzl tphz tplz Propagation elay, Clock to QA or QH (Figure 1) Propagation elay, Clock to QA or QH (Figure 1) Propagation elay, Clock to QA thru QH (Figure 1) Propagation elay, Clock to QA thru QH (Figure 1) Propagation elay, OE1, OE2 to QA thru QH (Figure 3) Propagation elay, OE1, OE2 to QA thru QH (Figure 3) Propagation elay, OE1, OE2 to QA thru QH (Figure 3) Propagation elay, OE1, OE2 to QA thru QH (Figure 3) Min Max Min Max CIN Maximum Input Capacitance pf Unit MHz C,VCC= V CP Power issipation Capacitance 17 pf * Voltage Range V is V ±.3 V Voltage Range V is V ±.5 V 4

5 TIMING REQUIREMENTS(CL=5pF,Input tr=tf=3. ) VCC * Guaranteed Limits Symbol Parameter V 25 C -4 C to 85 C tsu tsu tsu tsu th th th th Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Minimum Setup Time, ata Inputs PA thru PH to Clock (Figure 4) Minimum Setup Time, ata Inputs SA, SH to Clock (Figure 4) Minimum Setup Time, Reset to Clock (Figure 2) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Hold Time, Clock to ata Inputs PA thru PH (Figure 4) Minimum Hold Time, Clock to ata Inputs SA, SH (Figure 4) Minimum Hold Time, Clock to Reset (Figure 2) tw Minimum Pulse Width, Clock (Figure 1) tw Minimum Pulse Width, Reset (Figure 2) * Voltage Range V is V ±.3 V Voltage Range V is V ±.5 V Unit 5

6 FUNCTION TABLE Inputs Respoe Mode Reset Mode Select Output Enables Clock Serial Inputs PA/ QA PB/ QB PC/ QC P/ Q PE/ QE PF/ QF PG/ QG PH/ QH QA QH S2 S1 OE1 OE2 A H Reset L X L L L X X L L L L L L L L L L Shift Right Shift Left Parallel Load L L X L L X X L L L L L L L L L L L H H X X X X X QA through QH=Z L L H L H H X X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H X H X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H L L X Shift Right: A FA =QA; FA FB =QB; etc H H L H X X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L X H X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L L L X Shift Left: H FH =QH; FH FG =QG; etc H H H X X X X Parallel Load:PN FN PA PH Hold H L L H X X X X Hold: QA through QH=Z; FN=FN PA PH H L L X H X X X Hold: QA through QH=Z; FN=FN PA PH H L L L L X X X Hold: QN =QH PA PH Z = high impedance = data on serial input F = flip-flop (see Logic iagram) When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state; however, sequential operation or clearing of the register is not affected. QB QB QB QG QG QG 6

7 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform 7

8 EXPANE LOGIC IAGRAM 8