Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS

Transcription

1 TECHNICAL DATA Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS IN74AC193 The IN74AC193 is identical in pinout to the LS/ALS193, HC/HCT193. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH traitio on the clock inputs. This counter may be preset by entering the desired data on the P, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.both a Terminal Count Down (TCD) and Terminal Count Up (TCU) Outputs are provided to enable cascading of both up and down counting functio. The TCD output produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TCU and TCD outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: 2. to 6. Low Input Current: 1. μa; 25 C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 ma ORDERING INFORMATION IN74AC193N Plastic IN74AC193D SOIC TA = -4 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =CC PIN 8 = GND 1

2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) -.5 to +7. IN DC Input oltage (Referenced to GND) -.5 to CC +.5 OUT DC Output oltage (Referenced to GND) -.5 to CC +.5 IIN DC Input Current, per Pin ± ma IOUT DC Output Sink/Source Current, per Pin ±5 ma ICC DC Supply Current, CC and GND Pi ±5 ma PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to + C TL Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) 75 5 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - mw/ C from 65 to 5 C SOIC Package: : - 7 mw/ C from 65 to 5 C mw 26 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) IN, OUT DC Input oltage, Output oltage (Referenced to GND) CC TJ Junction Temperature (PDIP) C TA Operating Temperature, All Package Types C IOH Output Current - High -24 ma IOL Output Current - Low 24 ma tr, tf Input Rise and Fall Time * (except Schmitt Inputs) CC =3. CC = CC = 4 25 / * IN from 3% to 7% CC This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range GND (IN or OUT) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC). Unused outputs must be left open. 2

3 DC ELECTRICAL CHARACTERISTICS(oltages Referenced to GND) CC Guaranteed Limits Symbol Parameter Test Conditio 25 C -4 C to 85 C IH IL OH Minimum High-Level Input oltage Maximum Low -Level Input oltage Minimum High-Level Output oltage OUT= or CC- 3. OUT= or CC- 3. IOUT -5 μa Unit * IN=IH or IL IOH=- ma IOH=-24 ma IOH=-24 ma OL Maximum Low-Level Output oltage IOUT 5 μa 3. IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) * IN=IH or IL IOL= ma IOL=24 ma IOL=24 ma IN=CC or GND ± ±1. μa OLD=1.65 Max 75 ma OHD=3.85 Min -75 ma IN=CC or GND 8. 8 μa * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2. ms, one output loaded at a time. Note: IIN and 3. are guaranteed to be less than or equal to the respective CC FUNCTION TABLE Inputs Mode MR PL CPU CPD H X X X Reset(Asyn.) L L X X Preset(Asyn.) L H H No Count L H H Count Up L H H Count Down L H H No Count X = don t care The IN74AC193 is an UP/DOWN MODULO- 16 Binary Counter. Logic equatio For Terminal Count: TCU = Q Q1 Q2 Q3 CPU TCD = Q Q1 Q2 Q3 CPD 3

4 AC ELECTRICAL CHARACTERISTICS(CL=5pF,Input tr=tf=3. ) CC * Guaranteed Limits Symbol Parameter 25 C -4 C to 85 C Unit fmax Maximum Clock Frequency (Figure 1) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, MR to Qn (Figure 5) Propagation Delay, MR to TCU (Figure 6) Propagation Delay, MR to TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Min Max Min Max CIN Maximum Input Capacitance pf MHz C,CC= CPD Power Dissipation Capacitance 45 pf * oltage Range is ±.3 oltage Range is ±.5 4

5 TIMING REQUIREMENTS(CL=5pF, Input tr=tf=3. ) CC * Guaranteed Limits Symbol Parameter 25 C -4 C to 85 C tsu Minimum Setup Time, Pn to PL (Figure 7) th Minimum Hold Time, PL to Pn (Figure 7) tw Minimum Pulse Width, PL (Figure 4) tw Minimum Pulse Width, CPU or CPD (Figure 1) tw Minimum Pulse Width, MR (Figure 5) trec trec Minimum Recovery Time, PL to CPU or CPD (Figure 5) Minimum Recovery Time, MR to CPU or CPD (Figure 5) * oltage Range is ±.3 oltage Range is ± Unit Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms 5

6 Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms TIMING DIAGRAM 6

7 EXPANDED LOGIC DIAGRAM 7