FACT DATA 5-1 SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
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- Claud Fleming
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1 The MC74AC160/74ACT160 and MC74AC162/74ACT162 are high-speed synchronous decade counters operating in e BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have o types of Count Enable inpu plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC160/74ACT160 has an asynchronous Master Reset input at overrides all oer inpu and forces e outpu LOW. The MC74AC162/74ACT162 has a Synchronous Reset input at overrides counting and parallel loading and allows all outpu to be simultaneously reset on e rising edge of e clock. Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 120 MHz Outpu Source/Sink 24 ma ACT160 and ACT162 Have TTL Compatible Inpu VCC TC Q0 Q1 Q2 Q3 CET PE SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER N SUFFIX CASE PLASTIC D SUFFIX CASE 751B-05 PLASTIC *R CP P0 P1 P2 P3 CEP GND PIN NAMES CEP CET CP MR SR P0 P3 PE Q0 Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input ( 160) Asynchronous Master Reset Input ( 162) Synchronous Reset Input Parallel Data Inpu Parallel Enable Input Flip-Flop Outpu Terminal Count Output 8 LOGIC SYMBOL PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3 *MR for 160 *SR for
2 FUNCTIONAL DESCRIPTION The MC74AC160/74ACT160 and MC74AC162/74ACT162 count modulo-10 in e BCD (8421) sequence. From state 9 (HLLH) ey increment to state 0 (LLLL). The clock inpu of all flip-flops are driven in parallel rough a clock buffer. Thus all changes of e Q outpu (except due to Master Reset of e 160) occur as a result of, and synchronous wi, e LOW-to-HIGH transition of e CP input signal. The circui have four fundamental modes of operation, in order of precedence: asynchronous reset ( 160), synchronous reset ( 162), parallel load, count-up and hold. Five control inpu Master Reset (MR, 160), Synchronous Reset (SR, 162), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine e mode of operation, as shown in e Mode Select Table. A LOW signal on MR overrides all oer inpu and asynchronously forces all outpu LOW. A LOW signal on SR overrides counting and parallel loading and allows all outpu to go LOW on e next rising edge of CP. A LOW signal on PE overrides counting and allows information on e Parallel Data (Pn) inpu to be loaded into e flip-flops on e next rising edge of CP. Wi PE and MR ( 160) or SR ( 162) HIGH, CEP and CET permit counting when bo are HIGH. Conversely, a LOW signal on eier CEP or CET inhibi counting. The MC74AC160/74ACT160 and MC74AC162/74ACT162 use D-type edge-triggered flip-flops and changing e SR, PE, CEP and CET inpu when e CP is in eier state does not cause errors, provided at e recommended setup and hold times, wi respect to e rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, e TC outpu can be used wi e CEP and CET inpu in o different ways. Please refer to e MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is erefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In e MC74AC160/74ACT160 and MC74AC162/74ACT162 decade counters, e TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to e normal sequence wiin o coun, as shown in e State Diagram. Logic Equations: Count Enable = CEP CET PE TC = Q0 Q 1 Q 2 Q 3 CET MODE SELECT TABLE *SR PE CET CEP Action on e Rising Clock Edge ( ) L X X X Reset (Clear) H L X X Load (Pn Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) STATE DIAGRAM *For 162 only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
3 LOGIC DIAGRAM P 0 P 1 P 2 P 3 PE CEP CET 162 ONLY TC CP CP 160 ONLY CP D CP D C D Q Q Q 0 Q0 DETAIL A DETAIL A DETAIL A DETAIL A MR 160 SR 162 Q 0 Q 1 Q 2 Q 3 Please note at is diagram is provided only for e understanding of logic operations and should not be used to estimate propagation delays. MAXIMUM RATINGS* Value VCC DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) 0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) 0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 ma Iout DC Output Sink/Source Current, per Pin ±50 ma ICC DC VCC or GND Current per Output Pin ±50 ma Tstg Storage Temperature 65 to +150 C * Maximum Ratings are ose values beyond which damage to e device may occur. Functional operation should be restricted to e Recommended Operating Conditions. 5-3
4 RECOMMENDED OPERATING CONDITIONS Min Typ Max VCC Supply Voltage AC ACT Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) 0 VCC V Input Rise and Fall Time (Note 1) tr, r tff AC Devices except Schmitt Inpu tr, tf 3.0 V V 40 ns/v 5.5 V 25 Input Rise and Fall Time (Note 2) 4.5 V 10 ACT Devices except Schmitt Inpu 5.5 V 8.0 TJ Junction Temperature (PDIP) 140 C TA Operating Ambient Temperature Range C IOH Output Current High 24 ma IOL Output Current Low 24 ma 1. V in from 30% to 70% V CC ; see individual Data Shee for devices at differ from e typical input rise and fall times. 2. V in from 0.8 V to 2.0 V; see individual Data Shee for devices at differ from e typical input rise and fall times. DC CHARACTERISTICS VCC 74AC Typ 74AC TA = 40 C Guaranteed Limi V ns/v Conditions VIH Minimum High Level VOUT = 0.1 V Input Voltage V or VCC 0.1 V VIL Maximum Low Level VOUT = 0.1 V Input Voltage V or VCC 0.1 V VOH Minimum High Level IOUT = 50 µa Output Voltage V *VIN = VIL or VIH ma V IOH 24 ma ma VOL Maximum Low Level IOUT = 50 µa Output Voltage V IIN IOLD IOHD Maximum Input Leakage Current Minimum Dynamic Output Current *VIN = VIL or VIH ma V IOL 24 ma ma 5.5 ±0.1 ±1.0 µa VI = VCC, GND ma VOLD = 1.65 V Max ma VOHD = 3.85 V Min ICC Maximum Quiescent Supply Current * All outpu loaded; resholds on input associated wi output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: I IN and I 3.0 V are guaranteed to be less an or equal to e respective 5.5 V V CC µa VIN = VCC or GND 5-4
5 MC74AC160 AC CHARACTERISTICS (For Figures and Waveforms See Section 3) fmax 74AC160 74AC160 Min Max Min Max Maximum Count Frequency CP to Qn (PE Input HIGH) CP to Qn (PE Input HIGH) CP to Qn (PE Input LOW) CP to Qn (PE Input LOW) CP to TC CP to TC CET to TC CET to TC MR to Qn ( AC160) MR to TC * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. MHz
6 MC74AC162 AC CHARACTERISTICS (For Figures and Waveforms See Section 3) fmax 74AC162 74AC162 Min Typ Max Min Max Maximum Count Frequency CP to Qn (PE Input HIGH) CP to Qn (PE Input HIGH) CP to Qn (PE Input LOW) CP to Qn (PE Input LOW) CP to TC CP to TC CET to TC CET to TC *Voltage Range 3.3 V is 3.0 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. MHz
7 MC74AC160 AC OPERATING REQUIREMENTS trec 74AC160 74AC160 Guaranteed Maximum Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE or SR to CP Hold Time, HIGH or LOW PE or SR to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Wid (Load) HIGH or LOW Clock Pulse Wid (Count) HIGH or LOW MR Pulse Wid, LOW ( AC160) Recovery Time MR to CP ( AC160) * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. 5-7
8 MC74AC162 AC OPERATING REQUIREMENTS Typ 74AC162 74AC162 Guaranteed Minimum Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP Clock Pulse Wid (Load) HIGH or LOW Clock Pulse Wid (Count) HIGH or LOW *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. 5-8
9 DC CHARACTERISTICS VCC 74ACT Typ 74ACT TA = 40 C Guaranteed Limi VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage V V V Conditions VOUT = 0.1 V or VCC 0.1 V VOUT = 0.1 V or VCC 0.1 V IOUT = 50 µa V VOL Maximum Low Level Output Voltage V *VIN = VIL or VIH 24 ma IOH 24 ma IOUT = 50 µa IIN Maximum Input Leakage Current *VIN = VIL or VIH V 24 ma IOL 24 ma 5.5 ±0.1 ±1.0 µa VI = VCC, GND ICCT Additional Max. ICC/Input ma VI = VCC 2.1 V IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current ma VOLD = 1.65 V Max ma VOHD = 3.85 V Min µa VIN = VCC or GND * All outpu loaded; resholds on input associated wi output under test. Maximum test duration 2.0 ms, one output loaded at a time. 5-9
10 MC74ACT160 AC CHARACTERISTICS (For Figures and Waveforms See Section 3) fmax Maximum Count Frequency CP to Qn (PE Input HIGH) CP to Qn (PE Input HIGH) CP to Qn (PE Input LOW) CP to Qn (PE Input LOW) CP to TC CP to TC CET to TC CET to TC MR to Qn ( AC160) MR to TC * Voltage Range 5.0 V is 5.0 V ±0.5 V. 74ACT160 74ACT160 Min Typ Max Min Max MHz
11 MC74ACT162 AC CHARACTERISTICS (For Figures and Waveforms See Section 3) fmax Maximum Count Frequency CP to Qn (PE Input HIGH) CP to Qn (PE Input HIGH) CP to Qn (PE Input LOW) CP to Qn (PE Input LOW) CP to TC CP to TC CET to TC CET to TC * Voltage Range 5.0 V is 5.0 V ±0.5 V. 3 74ACT162 74ACT162 Min Typ Max Min Max MHz
12 MC74ACT160 AC OPERATING REQUIREMENTS trec Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE or MR to CP Hold Time, HIGH or LOW PE or MR to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Wid (Load) HIGH or LOW Clock Pulse Wid (Count) HIGH or LOW MR Pulse Wid, LOW ( ACT160) Recovery Time MR to CP ( ACT160) * Voltage Range 5.0 V is 5.0 V ±0.5 V. Typ 74ACT160 74ACT160 Guaranteed Maximum
13 MC74ACT162 AC OPERATING REQUIREMENTS Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP Setup Time, HIGH or LOW CET to CP Hold Time, HIGH or LOW CET to CP Clock Pulse Wid (Load) HIGH or LOW Clock Pulse Wid (Count) HIGH or LOW * Voltage Range 5.0 V is 5.0 V ±0.5 V. Typ 74ACT162 74ACT162 Guaranteed Maximum CAPACITANCE Value Typ Test Conditions CIN Input Capacitance 4.5 pf VCC = 5.0 V CPD Power Dissipation Capacitance 45 pf VCC = 5.0 V 5-13
14 OUTLINE DIMENSIONS 16 A 1 8 H G F 9 D 16 PL B S C K 0.25 (0.010) M T SEATING T PLANE A M N SUFFIX PLASTIC DIP PACKAGE CASE ISSUE R J L M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC H BSC 1.27 BSC J K L M S T SEATING PLANE G A D 16 PL K B D SUFFIX PLASTIC SOIC PACKAGE CASE 751B 05 ISSUE J P 8 PL 0.25 (0.010) M B S C 0.25 (0.010) M T B S A S M R X 45 J F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC BSC J K M P R Motorola reserves e right to make changes wiout furer notice to any produc herein. Motorola makes no warranty, representation or guarantee regarding e suitability of i produc for any particular purpose, nor does Motorola assume any liability arising out of e application or use of any product or circuit, and specifically disclaims any and all liability, including wiout limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical exper. Motorola does not convey any license under i patent righ nor e righ of oers. Motorola produc are not designed, intended, or auorized for use as componen in systems intended for surgical implant into e body, or oer applications intended to support or sustain life, or for any oer application in which e failure of e Motorola product could create a situation where personal injury or dea may occur. Should Buyer purchase or use Motorola produc for any such unintended or unauorized application, Buyer shall indemnify and hold Motorola and i officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, cos, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea associated wi such unintended or unauorized use, even if such claim alleges at Motorola was negligent regarding e design or manufacture of e part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Taumi SPD JLDC, Toshikau Ouki, P.O. Box 20912; Phoenix, Arizona F Seibu Buuryu Center, Taumi Koto Ku, Tokyo 135, Japan MFAX: RMFAX0@ .sps.mot.com TOUCHTONE (602) HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong MC74AC160/D
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