HFA GHz - 2.5GHz 250mW Power Amplifier. Features. Applications. Ordering Information. Functional Block Diagram. Pinout

Transcription

1 Data Sheet July 99 File Number..GHz -.GHz mw Power Amplifier The Intersil.GHz PRISM chip set is a highly integrated five-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA9.GHz-.GHz, mw power amplifier is one of the five chips in the PRISM chip set (see the Typical Application Diagram). The Intersil HFA9 is an integrated power amplifier with transmit/receive switch in a low cost SSOP plastic package. The power amplifier delivers +db of gain with high efficiency and can be operated with voltages as low as.v. The power amplifier switch is fully monolithic and can be controlled with CMOS logic levels. The HFA9 is ideally suited for QPSK, BPSK or other linearly modulated systems in the.ghz Industrial, Scientific, and Medical (ISM) frequency band. It can also be used in GFSK systems where levels of +dbm are required. Typical applications include Wireless Local Area Network (WLAN) and wireless portable data collection. REMEMBER: Always apply Negative power to the VG pins before applying the Positive V DD bias. Failure to do so may result in the destruction of the HFA9 Power Amplifier. Features Highly Integrated Power Amplifier with T/R Switch Operates Over.V to Supply Voltage High Linear Output Power (P db : +dbm) Individual Gate Control for Each Amplifier Stage Low Cost SSOP- Plastic Package Applications Systems Targeting IEEE. Standard TDD Quadrature-Modulated Communication Systems Wireless Local Area Networks PCMCIA Wireless Transceivers ISM Systems TDMA Packet Protocol Radios PCS/Wireless PBX Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. HFA9IA - to Ld SSOP M. HFA9IA9 - to Tape and Reel Pinout HFA9 (SSOP) TOP VIEW Functional Block Diagram T/R CNTRL V DDX (+) V GX (-) V DD TR T/R CNTRL RF OUT STAGE BIAS CONTROL RX OUT V DD RX OUT V G 9 9 STAGE STAGE STAGE RF_OUT TO ANTENNA V DD V DD V G V G -9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or --9 Copyright Intersil Corporation 999 PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

2 Typical Application Diagram HFA HSP (FILE# ) TUNE/SELECT (FILE# ) HFA (NOTE) (FILE# ) HFA UP/DOWN CONVERTER (FILE# ) o /9 o M U X I M U X RXI RXQ RSSI A/D A/D A/D TXI DE- SPREAD CCA DPSK DEMOD. MAC-PHY INTERFACE DATA TO MAC CTRL RFPA HFA9 (FILE# ) VCO VCO Q TXQ SPREAD DPSK MOD. DUAL SYNTHESIZER HFA (FILE# ) QUAD IF MODULATOR DSSS BASEBAND PROCESSOR PRISM CHIP SET FILE # NOTE: Required for systems targeting. specifications. TYPICAL TRANSCEIVER APPLICATION USING THE HFA9 For additional information on the PRISM chip set, call () - to access Intersil AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. The four-digit file numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit -

3 Absolute Maximum Ratings Maximum Input Power (Note ) dbm Operating Voltages (Notes, ) V DD = V, V GG = -V Operating Conditions Temperature Range o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) SSOP Package Maximum Storage Temperature Range o C to o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = o C, Z = Ω, V DD = +, P IN = -dbm, f =.GHz, Unless Otherwise Specified PARAMETER MIN TYP MAX UNITS POWER AMPLIFIER Linear Gain db VSWR In/Out -.: - Input Return Loss db Output Return Loss db Output Power at P db.. - dbm Second Harmonic at P db - - dbc Third Harmonic at P db dbc IDD at PdB (VDD + VDD + VDD) - ma NOTES:. Ambient temperature (T A ) = o C.. V DD + V GG not to exceed V. Pin Description PINS SYMBOL DESCRIPTION DC and RF Ground. DC and RF Ground. DC and RF Ground. DC and RF Ground. DC and RF Ground. DC and RF Ground. DC and RF Ground. RX OUT Output of T/R Switch for receive mode. 9 V G Negative bias control for the second PA stage, adjusted to set V DD quiescent bias current, which is typically ma. Typical voltage at pin = -.. Input impedance: > MΩ. DC and RF Ground. V DD Positive bias for the first stage of the PA,.V to. DC and RF Ground. DC and RF Ground. V G Negative bias control for the first PA stage, adjusted to set V DD quiescent bias current, which is typically ma. Typical voltage at pin = -.. Input impedance: > MΩ. RF Input of the Power Amplifier. DC and RF Ground. -

4 Pin Description (Continued) PINS SYMBOL DESCRIPTION V G Negative bias control for the third PA stage, adjusted to set V DD quiescent bias current, which is typically 9mA. Typical voltage at pin = -.9. Input impedance: > MΩ. V DD Positive bias for the second stage of the PA..V to. 9- DC and RF Ground. V DD Positive bias for the third stage of the PA..V to. DC and RF Ground. RF OUT RF output of T/R switch and power amplifier for transmit mode. T/R CTRL V for transmit mode, + for receive mode. Low < =.V, high > = V DD -.V. V DD TR V DD for T/R switch. DC and RF Ground. NOTE: Process variation will effect V G voltage requirement to develop 9mA stage quiescent current, maximum range = -.9V to -.. Typical Performance Curves Power Amplifier Small Signal Performance NOTE: All data measured at T A = o C and V G,V G and V G adjusted for first stage quiescent current of ma, second stage current of ma and third stage current of 9mA, respectively V DD = V DD = V DD - GAIN (db) RETURN LOSS (db) FIGURE. LINEAR GAIN FIGURE. INPUT MATCH - RETURN LOSS (db) FIGURE. OUTPUT MATCH -

5 Typical Performance Curves (Continued) Power Amplifier CW Performance at Various Supply Voltages NOTE: All data measured at T A = o C and V G,V G and V G adjusted for first stage quiescent current of ma, second stage current of ma and third stage current of 9mA, respectively..ghz, V DD = V DD = V DD.GHz, V DD = V DD = V DD POWER (dbm) EFFICIENCY (%) POWER INPUT (dbm) FIGURE. POWER OUTPUT INPUT POWER (dbm) FIGURE. POWER ADDED EFFICIENCY - COMPRESSION (dbm) GHz, V DD = V DD = V DD INPUT POWER (dbm) FIGURE. GAIN COMPRESSION Power Amplifier Temperature Performance NOTE: All data measured at T A = o C and V G,V G and V G adjusted for first stage quiescent current of ma, second stage current of ma and third stage current of 9mA, respectively..ghz, V DD = V DD = V DD = + GAIN (db) o C o C - o C POWER (dbm) o C - o C o C V DD = V DD = V DD = FIGURE. LINEAR GAIN INPUT POWER (dbm) FIGURE. POWER OUTPUT -

6 Typical Performance Curves (Continued) COMPRESSION (db) o C o C o C -.GHz, V DD = V DD = V DD = INPUT POWER (dbm) FIGURE 9. GAIN COMPRESSION Power Amplifier Spurious Response at Various Supply Voltages NOTE: All data measured at T A = o C and V G,V G and V G adjusted for first stage quiescent current of ma, second stage current of ma and third stage current of 9mA, respectively..ghz, TONE SPACING khz.ghz, V DD = V DD = V DD IMR (dbc) dbc 9 FUNDAMENTAL P OUT OF TONES (dbm) FIGURE. THIRD ORDER INTERMODULATION RATIO 9 FUNDAMENTAL P OUT (dbm) FIGURE. SECOND HARMONIC RATIO dbc.ghz, V DD = V DD = V DD 9 FUNDAMENTAL P OUT (dbm) FIGURE. THIRD HARMONIC RATIO -

7 Typical Performance Curves (Continued) Transmit/Receive Switch Performance NOTE: All data measured with V DD TR = +, T A = o C. - INSERTION LOSS (db) ISOLATION (db) RETURN LOSS (db) INPUT OUTPUT FIGURE. RECEIVE MODE T/R INSERTION LOSS/ISOLATION FIGURE. RECEIVE MODE T/R SWITCH MATCH Typical Application Example C C V DD (T/R ANT) C C T/R CNTRL C RF OUT (Ω TRANSMISSION LINE) RX OUT (Ω TRANSMISSION LINE) V G (-) R V DD (+) C C R C C C 9 9 C C C 9 C C C C R R V DD (+) V DD (+) V G (-) V G (-) R R C C (Ω TRANSMISSION LINE) EXTERNAL CIRCUITRY PARTS LIST LABEL VALUE PURPOSE C -C, C, C pf Bypass (GHz) C -C pf DC Block C -C pf Bypass (MHz) C -C.µF Bypass (khz) R, R.kΩ FET Gate Divider R, R kω Network R kω R kω NOTE: All off-chip components are low cost surface mount components obtainable from multiple sources. (.in x.in or.in x.in.) -

8 Typical Application Diagram PAPE STEP TO +. PAPE MMBTALT MOTOROLA SOT.K K V CC Positive Supply, Single Stage Adjustment Circuit V CC G S G S pf pf RFK99 HFA9 V DD T/R D D D D L BEAD T/R CTRL RF OUT pf V DD.µF.µF RX OUT.K 9 V G 9 RF OUT HFA LNA nh pf V CC.µF.K Ω V DD V G V DD V G.µF pf K.µF ICLSIBA SUPER VOLTAGE CONVERTER +IN -OUT + TO -V CONVERTER -.µf + TANTL K MMBT ALT MOTOROLA +. V POWER UP TIMING PAPE TRANSMIT ENABLED RECEIVE ENABLED V CC V CC = + V CC = +..µf TANTL TRUTH TABLE PAPE TR/CTRL MODE V + V CC Low () High () Receive High () Low () Transmit V ms MIN -

9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box, Mail Stop - Melbourne, FL 9 TEL: () - FAX: () - For information regarding Intersil Corporation and its products, see web site EUROPE Intersil SA Mercure Center, Rue de la Fusee Brussels, Belgium TEL: ().. FAX: ()... ASIA Intersil (Taiwan) Ltd. F-, No. Fu Hsing North Road Taipei, Taiwan Republic of China TEL: () 9 FAX: () 9 -