2 GHz to 28 GHz, GaAs phemt MMIC Low Noise Amplifier HMC7950

Transcription

1 Data Sheet FEATURES Output power for db compression (PdB): 6 dbm typical Saturated output power (PSAT): 9. dbm typical Gain: db typical Noise figure:. db typical Output third-order intercept (IP3): 6 dbm typical Supply voltage: V at 6 ma Ω matched input/output APPLICATIONS Test instrumentation Military and space GENERAL DESCRIPTION The HMC79 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (phemt), monolithic microwave integrated circuit (MMIC). The HMC79 is a wideband low noise amplifier that operates between GHz and GHz. The amplifier typically provides db of gain,. db of noise figure, 6 dbm of output IP3, and 6 dbm of output power for db gain compression, requiring 6 ma from a V supply. The HMC79 GHz to GHz, GaAs phemt MMIC Low Noise Amplifier HMC79 V DD 3 FUNCTIONAL BLOCK DIAGRAM V GG 6 HMC79 RFIN RFOUT 6 Figure. PACKAGE BASE is self biased with only a single positive supply needed to achieve a drain current, IDD, of 6 ma. The HMC79 also has a gain control option, VGG. The HMC79 amplifier input/outputs are internally matched to Ω and dc blocked. It comes in a 6 mm 6 mm, 6-terminal LCC SMT ceramic package that is easy to handle and assemble Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 HMC79 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... 3 GHz to GHz Frequency Range... 3 GHz to GHz Frequency Range... 3 GHz to GHz Frequency Range... DC Specifications... Absolute Maximum Ratings... Thermal Resistance... Data Sheet ESD Caution... Pin Configuration and Function Descriptions...6 Interface Schematics...6 Typical Performance Characteristics...7 Theory of Operation... Applications Information... 3 Evaluation Board... Evaluation Board Schematic... Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 9/7 Rev. to Rev. A Added Figure 37; Renumbered Sequentially... /7 Revision : Initial Version Rev. A Page of 6

3 Data Sheet HMC79 SPECIFICATIONS GHz TO GHz FREQUENCY RANGE TA = C, VDD = V, VGG = open, unless otherwise stated. When using VGG, it is recommended to limit VGG from V to +.6 V. POUT is output power. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE GHz GAIN 3.. db Gain Variation Over Temperature. db/ C RETURN LOSS Input db Output 3 db OUTPUT Output Power for db Compression PdB 3 6. dbm Saturated Output Power PSAT. dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = dbm 6. dbm NOISE FIGURE NF 3.. db GHz TO GHz FREQUENCY RANGE TA = C, VDD = V, VGG = open, unless otherwise stated. When using VGG, it is recommended to limit VGG from V to +.6 V. POUT is output power. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE GHz GAIN 3.3 db Gain Variation Over Temperature.7 db/ C RETURN LOSS Input db Output db OUTPUT Output Power for db Compression PdB 3 6 dbm Saturated Output Power PSAT 9. dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = dbm 6 dbm NOISE FIGURE NF. 3. db Rev. A Page 3 of 6

4 HMC79 Data Sheet GHz TO GHz FREQUENCY RANGE TA = C, VDD = V, VGG = open, unless otherwise stated. When using VGG, it is recommended to limit VGG from V to +.6 V. POUT is output power. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE GHz GAIN 3 6. db Gain Variation over Temperature. db/ C RETURN LOSS Input 9 db Output 6 db OUTPUT Output Power for db Compression PdB. dbm Saturated Output Power PSAT 7 dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = dbm dbm NOISE FIGURE NF. db DC SPECIFICATIONS Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY CURRENT Total Supply Current IDD 6 ma Total Supply Current vs. VDD IDD = ma 3 V IDD = 6 ma V IDD = 6 ma V IDD = 66 ma 6 V IDD = 69 ma 7 V SUPPLY VOLTAGE VDD 3 7 V VGG PIN VGG Normal condition is VGG = open..6 V Rev. A Page of 6

5 Data Sheet ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage (VDD) V Second Gate Bias Voltage (VGG). V to +3 V Radio Frequency Input Power (RFIN) dbm Channel Temperature 7 C Continuous Power Dissipation (PDISS),. W TA = C (Derate 7. mw/ C Above C) Maximum Peak Reflow Temperature (MSL3) 6 C Storage Temperature Range 6 C to + C Operating Temperature Range C to ESD Sensitivity, Human Body Model (HBM) V (Class A) See the Ordering Guide section for more information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. HMC79 THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θjc is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type θjc Unit EP-6- C/W Channel to ground pad. See JEDEC Standard JESD- for additional information on optimizing the thermal impedance ESD CAUTION Rev. A Page of 6

6 HMC79 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD RFOUT 3 HMC79 TOP VIEW (Not to Scale) 9 Figure. Pin Configuration Table 7. Pin Function Descriptions Pin Mnemonic Description,,, 9,,,, 6 No Internal Connection. Note that data shown herein was measured with these pins externally connected to RF/dc ground. See Figure 3 for the interface schematic. 3 VDD Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDD). See Figure for the interface schematic. VGG Gain Control. This pin is dc-coupled and accomplishes gain control by reducing the internal voltage and becoming more negative. See Figure for the interface schematic., 7, 3, These pins must be connected to RF/dc ground. See Figure 3 for the interface schematic. 6 RFIN Radio Frequency (RF) Input. This pin is ac-coupled, but has a large resistor to for ESD protection, and matched to Ω. See Figure 6 for the interface schematic. RFOUT RF Output. This pin is ac-coupled, but has a large resistor to for ESD protection, and matched to Ω. See Figure 7 for the interface schematic. EPAD () Exposed Pad (Ground). The exposed pad must be connected to RF/dc ground. See Figure 3 for the interface schematic. INTERFACE SCHEMATICS V GG RFIN NOTES. = NO INTERNAL CONNECTION. NOTE THAT DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS EXTERNALLY CONNECTED TO RF/DC GROUND.. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. - Figure 3. Interface Schematic V DD -7 RFIN -3 Figure 6. RFIN Interface Schematic - Figure. VDD Interface Schematic V GG RFOUT Figure 7. RFOUT Interface Schematic -6 - Figure. VGG Interface Schematic Rev. A Page 6 of 6

7 Data Sheet HMC79 TYPICAL PERFORMANCE CHARACTERISTICS RESPONSE (db) GAIN (db) 6 C + C S S S Figure. Response (Gain and Return Loss) vs. Frequency Figure. Gain vs. Frequency at Various Temperatures C + C C + C RETURN LOSS (db) RETURN LOSS (db) Figure 9. Input Return Loss vs. Frequency at Various Temperatures Figure. Output Return Loss vs. Frequency at Various Temperatures - 6 C + C 7 6 C + C NOISE FIGURE (db) 3 PdB (dbm) Figure. Noise Figure vs. Frequency at Various Temperatures Figure 3. PdB vs. Frequency at Various Temperatures -3 Rev. A Page 7 of 6

8 HMC79 Data Sheet C + C 9 7 V V 6V 9 6 P SAT (dbm) 7 6 PdB (dbm) Figure. PSAT vs. Frequency at Various Temperatures Figure 7. PdB vs. Frequency at Various Supply Voltages 3 V V 6V 3 C + C P SAT (dbm) IP3 (dbm) FREQUENCY (dbm) - Figure. PSAT vs. Frequency at Various Supply Voltages Figure. Output IP3 vs. Frequency at Various Temperatures, POUT/Tone = dbm 3 V V 6V 6 GHz GHz 6GHz GHz GHz 6 IP3 (dbm) IMD3 (dbc) FREQUENCY (dbm) Figure 6. Output IP3 vs. Frequency at Various Supply Voltages POUT/Tone = dbm P OUT /TONE (dbm) Figure 9. Output Third-Order Intermodulation Distortion (IMD3) vs. POUT/Tone at Various Frequencies, VDD = V -9 Rev. A Page of 6

9 Data Sheet HMC79 IMD3 (dbc) 6 3 GHz GHz 6GHz GHz GHz POWER DISSIPATION (W) GHz GHz 6GHz GHz GHz I DD AT 6GHz I DD (ma) P OUT /TONE (dbm) Figure. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = V INPUT POWER (dbm) Figure 3. Power Dissipation and IDD vs. Input Power at Various Frequencies, 6 GHz, TA = C -3 6 GHz GHz 6GHz GHz GHz 76 7 GHz GHz 6GHz GHz GHz IMD3 (dbc) I DD (ma) P OUT /TONE (dbm) Figure. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = 6 V INPUT POWER (dbm) Figure. IDD vs. Input Power at Various Frequencies - C + C I GG I DD 7 6 REVERSE ISOLATION (db) 3 I GG (ma) 3 6 I DD (ma) Figure. Reverse Isolation vs. Frequency at Various Temperatures V GG (V) Figure. IGG and IDD vs. VGG at GHz, Input Power (PIN) = dbm - Rev. A Page 9 of 6

10 HMC79 Data Sheet GAIN (db) V V.6V.V 3.V.V V.6V V.V.V.V.6V 3-6 PdB (dbm).v.v.v.v.6v.v.v.6v.v V V.V Figure 6. Gain vs. Frequency at Various VGG Voltage Levels Figure 9. PdB vs. Frequency at Various VGG Voltage Levels V.6V.V.V V.V.V V.V V.6V.V.6V 6.V.V.6V.V.V V.V.V.V.6V V.V RETURN LOSS (db) P SAT (dbm) 6 3 Figure 7. Input Return Loss vs. Frequency at Various VGG Voltage Levels Figure 3. PSAT vs. Frequency at Various VGG Voltage Levels -3 RETURN LOSS (db) V.6V.V.V V.V.V V.V V.6V.V.6V IP3 (dbm) 3 3 Figure. Output Return Loss vs. Frequency at Various VGG Voltage Levels -.V.V.V.V.6V.6V.V V V.V.V Figure 3. Output IP3 vs. Frequency at Various VGG Voltage Levels, POUT/Tone = dbm -3 Rev. A Page of 6

11 Data Sheet HMC79 GAIN (db) SECOND HARMO (dbc) V GG (V) C + C Figure 3. Gain vs. VGG at GHz Figure 3. Second Harmonic vs. Frequency at Various Temperatures, POUT = dbm IP3 (dbm) 6 6 SECOND HARMO (dbc) 3 3 dbm dbm V GG (V) Figure 33. Output IP3 vs. VGG at GHz Figure 36. Second Harmonic vs. Frequency at Various Output Powers C + C IP (dbm) PHASE NOISE (dbc/hz) k k k M OFFSET FREQUENCY (Hz) -37 Figure 3. Output IP vs. Frequency at Various Temperatures, POUT/Tone = dbm Figure 37. Additive Phase Noise vs. Offset Frequency, RF Frequency = GHz, RF Input Power =. dbm (PdB) Rev. A Page of 6

12 HMC79 THEORY OF OPERATION The HMC79 is a GaAs, phemt, MMIC low noise amplifier. Its basic architecture is that of a single-supply, biased cascode distributed amplifier with an integrated RF choke for the drain. The cascode distributed architecture uses a fundamental cell consisting of a stack of two field effect transistors (FETs) with the source of the upper FET connected to the drain of the lower FET. The fundamental cell is then duplicated several times, with a transmission line feeding the RFIN signal to the gates of the lower FETs and a separate transmission line interconnecting the drains of the upper FETs and routing the amplified signal to the RFOUT pin. Additional circuit design techniques around each cell optimize the overall performance for broadband operation. The major benefit of this architecture is that high performance is maintained across a bandwidth far greater than a single instance of the fundamental cell can provide. A simplified schematic of this architecture is shown in Figure 3. Data Sheet Although the gate bias voltages of the upper FETs are set internally by a resistive voltage divider connected to VDD, the VGG pin provides the user with an optional means of changing the gate bias of the upper FETs. Application of a voltage to VGG allows the user to change the voltage output by the resistive divider, altering the gate bias of the upper FETs and thus changing the gain. Application of VGG voltages across the range of. V to +.6 V affects gain changes of approximately 3 db, depending on the frequency. Increasing the voltage applied to VGG increases the gain, whereas decreasing the voltage decreases the gain. For VDD =. V (nominal), the resulting VGG open circuit voltage is approximately. V. V DD TRANSMISSION LINE RFOUT V GG RFIN TRANSMISSION LINE -36 Figure 3. Architecture and Simplified Schematic Rev. A Page of 6

13 Data Sheet APPLICATIONS INFORMATION Capacitive bypassing is recommended for VDD, as shown in the typical application circuit in Figure 39. Gain control is possible through the application of a dc voltage to VGG. If gain control is used, capacitive bypassing of VGG is recommended as shown in the typical application circuit. If gain control is not used, VGG can be either left open or capacitively bypassed as shown in Figure 39. The recommended bias sequence during power-up is as follows:. Set VDD to. V (this results in an IDD near its specified typical value).. If the gain control function is to be used, apply a voltage within the range of. V to +.6 V to VGG until the desired gain setting is achieved. 3. Apply the RF input signal. HMC79 The recommended bias sequence during power-down is as follows:. Turn off the RF input signal.. Remove the VGG voltage, or set it to V. 3. Set VDD to V. Power-up and power-down sequences can differ from the ones described, although care must always be taken to ensure adherence to the values shown in the Absolute Maximum Ratings section. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit as configured on the HMC79 evaluation board. The bias conditions shown in the Specifications section are recommended to optimize the overall performance. Operation using other bias conditions may result in performance that differs from the data shown in this data sheet. V DD.7µF nf pf 3 V GG +.7µF nf pf 6 RFIN 6 RFOUT PACKAGE BASE -37 Figure 39. Typical Application Circuit Rev. A Page 3 of 6

14 HMC79 EVALUATION BOARD The HMC79 evaluation board is a -layer board fabricated using Rogers 3 and using best practices for high frequency RF design. The RF input and RF output traces have a Ω characteristic impedance. The evaluation board and populated components are designed to operate over the ambient temperature range of C to. For the proper bias sequence, see the Applications Information section. The evaluation board schematic is shown in Figure. A fully populated and tested evaluation board, shown in Figure, is available from Analog Devices, Inc., upon request. RFIN C9-3 REV B J VGG C7 C C C VGG H79 C C3 C J3 VDD C6 U ANALOG DEVICES HMC79LS6 EVAL RFOUT Figure. Evaluation PCB Data Sheet -3 Table. Bill of Materials for Evaluation PCB EVHMC79LS6 Item Description RFIN, RFOUT PCB mount, K connector, SRI Part Number C, C7 pf capacitor, %, V, CG, package C3, C nf capacitor, %, 6 V, X7R, package C, C9.7 µf tantalum capacitor, %, V, 6 package U Amplifier, HMC79LS6 PCB Evaluation PCB; circuit board material: Rogers 3 VDD, VGG DC pins, Molex Part Number 779- C, C, C6, J3, J, VGG Do not install (DNI) Rev. A Page of 6

15 Data Sheet HMC79 EVALUATION BOARD SCHEMATIC VGG 3 VDD 3 C9.7µF C pf C3 nf + C.7µF C nf C7 pf 3 V GG V DD 6 RFIN 6 RFIN HMC79LS6 RFOUT RFOUT 7 EPAD 3 9 VGG DNI 3 C DNI C DNI + C6 DNI J3 DNI THRU_CAL J DNI -39 Figure. Evaluation Board Schematic Rev. A Page of 6

16 HMC79 Data Sheet OUTLINE DIMENSIONS PIN INDICATOR SQ BSC SQ Figure. 6-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS] (EP-6-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range MSL Rating Lead Finish Package Description Package Option Branding 3 HMC79LS6 C to MSL3 Au 6-Terminal LCC_HS EP-6- HMC79LS6TR C to MSL3 Au 6-Terminal LCC_HS EP-6- EVHMC79LS6 PKG-93. BSC TOP VIEW.9 BSC SIDE VIEW..37. MAX COPLANARITY. BOTTOM VIEW Evaluation PCB The HMC79LS6 and HMC79LS6TR are RoHS compliant parts, made of low stress injection molded plastic. See the Absolute Maximum Ratings section for further information on the moisture sensitivity level (MSL) rating. 3 XXXX is the four-digit lot number FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET B H79 XXXX H79 XXXX 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--9/7(A) Rev. A Page 6 of 6