71 GHz to 76 GHz, 1 W E-Band Power Amplifier with Power Detector ADMV7710

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1 Data Sheet FEATURES Gain: db typical Output power for db compression: dbm typical Saturated output power: 29 dbm typical Output third-order intercept: dbm typical Input return loss: 8 db typical Output return loss: db typical DC supply: 4 V at 8 ma No external matching required Die size: mm mm. mm APPLICATIONS E-band communication systems High capacity wireless backhaul radio systems Test and measurement 7 GHz to 76 GHz, W E-Band Power Amplifier with Power Detector ADMV77 GENERAL DESCRIPTION The ADMV77 is an integrated, E-band, gallium arsenide (GaAs), pseudomorphic, high electron mobility tranfer (phemt), mono-lithic microwave integrated circuit (MMIC), medium power amplifier with an on-chip, temperature compensated power detector that operates from 7 GHz to 76 GHz. The ADMV77 provides db of gain, dbm of output power at db compression, and 29 dbm of saturated output power at % power added efficiency from a 4 V power supply. The ADMV77 exhibits excellent linearity and is optimized for E-band communications and high capacity, wireless backhaul radio systems. The amplifier configuration and high gain make the device an excellent candidate for last stage signal amplification before the antenna. All data is taken with the chip in a Ω test fixture connected via a 3 mil wide. mil thick 7 mil long ribbon on each port. The ADMV77 is available in a 4-pad bare die (CHIP) and operates over the C to +8 C temperature range. FUNCTIONAL BLOCK DIAGRAM VGGA VDDA VGG2A VDD2A VGG3A VDD3A VGG4A VDD4A ADMV77 RFOUT RFIN VGGB 4 VDDB VGG2B VDD2B VGG3B 3 VDD3B 29 VGG4B 27 VDD4B VDET VREF Figure. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADMV77 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... Interface Schematics... 6 Typical Performance Characteristics... 7 Data Sheet Theory of Operation... 4 Applications Information... Assembly Diagram... 6 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs... 7 Handling Precautions... 7 Mounting... 7 Wire Bonding... 7 Outline Dimensions... 8 Ordering Guide... 8 REVISION HISTORY 2/8 Rev. to Rev. A Changes to Figure Changes to Figure 43 and Figure Added Figure 4; Renumbered Sequentially... 3 Changes to Ordering Guide /8 Revision : Initial Version Rev. A Page 2 of 8

3 Data Sheet ADMV77 SPECIFICATIONS TA = C, VDDxA and VDDxB = 4 V, I DD = 8 ma, unless otherwise noted. Table. Parameter Symbol Min Typ Max Unit OPERATING CONDITIONS Frequency Range 7 76 GHz PERFORMANCE Gain 2 db Gain Variation over Temperature.2 db/ C Output Power for db Compression OPdB dbm Saturated Output Power PSAT 29 dbm Output Third-Order Intercept at Maximum Gain OIP3 dbm Power Added Efficiency PAE % Input Return Loss 8 db Output Return Loss db POWER SUPPLY Total Drain Current 2 IDD 8 ma Data taken at output power (POUT) = 4 dbm per tone, MHz spacing. 2 Adjust the VGGxA and VGGxB pads from 2 V to V to achieve the total drain current (IDD) = 8 ma. Rev. A Page 3 of 8

4 ADMV77 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Drain Bias Voltage (VDDA to VDD4A, VDDB to VDD4B) Gate Bias Voltage (VGGA to VGG4A, VGGB to VGG4B) Maximum Junction Temperature (to Maintain Million Hours Mean Time to Failure (MTTF)) Operating Temperature Range Storage Temperature Range Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Rating 4. V 3 V to V 7 C C to +8 C 6 C to + C V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Data Sheet THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θjc is the junction to case (or die to package) thermal resistance. Table 3. Thermal Resistance Package Type θjc Unit C C/W Based on the ATROX 8HTV as the die attach epoxy. ESD CAUTION Rev. A Page 4 of 8

5 Data Sheet ADMV77 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGGA VDDA VGG2A VDD2A VGG3A VDD3A VGG4A VDD4A RFOUT RFIN ADMV77 TOP VIEW (Not to Scale) VGGB 4 VDDB VGG2B VDD2B VGG3B 3 VDD3B 29 VGG4B 27 VDD4B VDET VREF Figure 2. Pad Configuration Table 4. Pad Function Descriptions Pad No. Mnemonic Description, 3,, 7, 9,, 3, Ground Connection (See Figure 3)., 7, 9,,,, 27, 29, 3,,,, 2 RFIN RF Input. AC-couple RFIN and match it to Ω (see Figure 4). 4, 8, 2, 6 VGGA to VGG4A First Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. 6,, 4, 8 VDDA to VDD4A First Stage Drain Bias Voltage for the Power Amplifier (See Figure ). 2 RFOUT RF Output. AC-couple RFOUT and match it to Ω (see Figure 6). 23 VREF Reference Voltage for the Power Detector (See Figure 7). VREF is the dc bias of the diode biased through an external resistor used for temperature compensation of VDET. Refer to the typical application circuit (see Figure 47) for the required external components. VDET Detector Voltage for the Power Detector (See Figure 7). VDET is the dc voltage representing the RF output power rectified by the diode, which is biased through an external resistor. Refer to the typical application circuit (see Figure 47) for the required external components.,,, VDD4B to VDDB Second Stage Drain Bias Voltage for the Power Amplifier (See Figure ).,,, 4 VGG4B to VGGB Second Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. Die Bottom Ground. The die bottom must be connected to the RF/dc ground (see Figure 3). Rev. A Page of 8

6 ADMV77 Data Sheet INTERFACE SCHEMATICS RFOUT Figure 3. Interface Schematic Figure 6. RFOUT Interface Schematic RFIN VREF, VDET Figure 4. RFIN Interface Schematic Figure 7. VREF, VDET Interface Schematic VDDA TO VDD4A VDDB TO VDD4B Figure. VDDA to VDD4A and VDDB to VDD4B Interface Schematic 648- VGGA TO VGG4A VGGB TO VGG4B Figure 8. VGGA to VGG4A and VGGB to VGG4B Interface Schematic Rev. A Page 6 of 8

7 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS RESPONSE (db) INPUT RETURN LOSS OUTPUT RETURN LOSS Figure 9. Broadband Gain and Return Loss Response vs. Frequency, IDD = 8 ma INPUT RETURN LOSS (db) T A = +8 C T A = + C T A = C ADMV Figure 2. Input Return Loss vs. Frequency over Various Temperatures, IDD = 8 ma (db) T A = +8 C T A = + C T A = C OUTPUT RETURN LOSS (db) T A = +8 C T A = + C T A = C Figure. Gain vs. Frequency over Various Temperatures, IDD = 8 ma Figure 3. Output Return Loss vs. Frequency over Various Temperatures, IDD = 8 ma (db) ma 6mA 7mA 8mA 9mA REVERSE ISOLATION (db) T A = +8 C T A = + C T A = C Figure. Gain vs. Frequency over IDD Figure 4. Reverse Isolation vs. Frequency over Various Temperatures, IDD = 8 ma Rev. A Page 7 of 8

8 ADMV77 Data Sheet OUTPUT PdB (dbm) T A = +8 C T A = + C T A = C OUTPUT PdB (dbm) ma 6mA 7mA 8mA 9mA Figure. Output PdB vs. Frequency over Various Temperatures, IDD = 8 ma Figure 8. Output PdB vs. Frequency over IDD P SAT (dbm) P SAT (dbm) T A = +8 C T A = + C T A = C ma 6mA 7mA 8mA 9mA Figure 6. PSAT vs. Frequency over Various Temperatures, IDD = 8 ma Figure 9. PSAT vs. Frequency over IDD OUTPUT IP3 (dbm) T A = +8 C T A = + C T A = C OUTPUT IP3 (dbm) ma 6mA 7mA 8mA 9mA Figure 7. Output IP3 vs. Frequency over Various Temperatures, IDD = 8 ma, POUT per Tone = 4 dbm Figure. Output IP3 vs. Frequency over IDD, POUT per Tone = 4 dbm 648- Rev. A Page 8 of 8

9 Data Sheet ADMV OUTPUT IP3 (dbm) 2dBm 4dBm 6dBm 8dBm dbm OUTPUT IP3 (dbm) ma 6mA 7mA 8mA 9mA Figure 2. Output IP3 vs. Frequency over POUT per Tone, IDD = 8 ma P OUT PER TONE (dbm) Figure. Output IP3 vs. POUT per Tone over IDD, RF = 7 GHz OUTPUT IP3 (dbm) ma 6mA 7mA 8mA 9mA OUTPUT IP3 (dbm) ma 6mA 7mA 8mA 9mA P OUT PER TONE (dbm) P OUT PER TONE (dbm) 648- Figure. Output IP3 vs. POUT per Tone over IDD, RF = 73. GHz Figure. Output IP3 vs. POUT per Tone over IDD, RF = 76 GHz 4 4 (db), OUTPUT PdB (dbm), P SAT (dbm) PdB P SAT DRAIN CURRENT (ma) Figure 23. Gain, Output PdB, and PSAT vs. Drain Current (IDD), RF = 7 GHz (db), OUTPUT PdB (dbm), P SAT (dbm) PdB P SAT DRAIN CURRENT (ma) Figure. Gain, Output PdB, and PSAT vs. Drain Current (IDD), RF = 73. GHz 648- Rev. A Page 9 of 8

10 ADMV77 Data Sheet 4 (db), OUTPUT PdB (dbm), P SAT (dbm) PdB P SAT DRAIN CURRENT (ma) Figure 27. Gain, Output PdB, and PSAT vs. Drain Current (IDD), RF = 76 GHz (db), P OUT (dbm), PAE (%) P OUT PAE I DD Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 76 GHz, IDD = 7 ma I DD (ma) 648- (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 7 GHz, IDD = 7 ma Figure 3. Gain, POUT, PAE, and IDD vs. Input Power, RF = 7 GHz, IDD = 8 ma (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) Figure 29. Gain, POUT, PAE, and IDD vs. Input Power, RF = 73. GHz, IDD = 7 ma Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 73. GHz, IDD = 8 ma 648- Rev. A Page of 8

11 Data Sheet ADMV77 (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 76 GHz, IDD = 8 ma Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 76 GHz, IDD = 9 ma. 4. (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) POWER DISSIPATION (W) GHz 72GHz 73GHz 74GHz 7GHz 76GHz Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 7 GHz, IDD = 9 ma Figure. Power Dissipation vs. Input Power over Various Frequencies, IDD = 7 ma, TA = 8 C (db), P OUT (dbm), PAE (%) P OUT PAE I DD I DD (ma) POWER DISSIPATION (W) GHz 72GHz 73GHz 74GHz 7GHz 76GHz Figure. Gain, POUT, PAE, and IDD vs. Input Power, RF = 73. GHz, IDD = 9 ma Figure. Power Dissipation vs. Input Power over Various Frequencies, IDD = 8 ma, TA = 8 C 648- Rev. A Page of 8

12 ADMV77 Data Sheet POWER DISSIPATION (W) GHz 72GHz 73GHz 74GHz 7GHz 76GHz OUTPUT IMD3 (dbc) 4 7GHz 72GHz 73GHz 74GHz 7GHz 76GHz Figure. Power Dissipation vs. Input Power over Various Frequencies, IDD = 9 ma, TA = 8 C OUTPUT POWER PER TONE (dbm) Figure 4. Upper Output Third-Order Intermodulation Distortion (IMD3) vs. Output Power (POUT) per Tone over Various Frequencies, IDD = 8 ma T A = +8 C T A = + C T A = C OUTPUT IMD3 (dbc) 4 7GHz 72GHz 73GHz 74GHz 7GHz 76GHz OUTPUT VOLTAGE (V) OUTPUT POWER PER TONE (dbm) Figure 4. Lower Output Third-Order Intermodulation Distortion (IMD3) vs. Output Power (POUT) per Tone over Various Frequencies, IDD = 8 ma OUTPUT POWER (dbm) Figure 42. Detector Output Voltage (VOUT) vs. Output Power over Various Temperatures, IDD = 8 ma, RF = 7 GHz Rev. A Page 2 of 8

13 Data Sheet ADMV77 OUTPUT VOLTAGE (V).. T A = +8 C T A = + C T A = C OUTPUT POWER (dbm) Figure 43. Detector Output Voltage (VOUT) vs. Output Power over Various Temperatures, IDD = 8 ma, RF = 73. GHz PHASE (Degrees) GHz PHASE DELTA 73GHz PHASE DELTA 76GHz PHASE DELTA 7GHz DELTA 73GHz DELTA 76GHz DELTA OUTPUT POWER (dbm) Figure 4. AM to PM Conversion vs. Output Power at Various Frequencies, TA = C (db) OUTPUT VOLTAGE (V).. T A = +8 C T A = + C T A = C OUTPUT POWER (dbm) Figure 44. Detector Output Voltage (VOUT) vs. Output Power over Various Temperatures, IDD = 8 ma, RF = 76 GHz Rev. A Page 3 of 8

14 ADMV77 THEORY OF OPERATION The circuit architecture of the ADMV77 power amplifier is shown in Figure 46. The ADMV77 uses four cascaded gain stages to form an amplifier with a combined gain of db and a saturated output power (PSAT) of 29 dbm. At the output of the last stage, a coupler taps off a small portion of the output signal. Data Sheet The coupled signal is presented to an on-chip diode detector for external monitoring of the output power. A matched reference diode is included to correct detector temperature dependencies. See the application circuit shown in Figure 47 for further details on biasing the different blocks and using the detector features. RFOUT RFIN Figure 46. Power Amplifier Circuit Architecture VDET VREF Rev. A Page 4 of 8

15 Data Sheet APPLICATIONS INFORMATION A typical application circuit for the ADMV77 is shown in Figure 47. Combine the supply lines as shown in the application circuit schematic to minimize the external component count and to simplify power supply routing. The ADMV77 uses several amplifier, detector, and attenuator stages. All stages use depletion mode phemt transistors. It is important to use the following power-up bias sequence to avoid transistor damage:. Apply a 2 V bias to the VGGA to VGG4A and VGGB to VGG4B pads. ADMV77 2. Apply 4 V to the VDDA to VDDB and VDDB to VDD4B pads. 3. Adjust VGGA to VGG4A and VGGB to VGG4B between 2 V and V to achieve a total amplifier drain current of 8 ma. To power down the ADMV77, follow the reverse procedure. For additional guidance on general bias sequencing, see the MMIC Amplifier Biasing Procedure application note. VDDA, VDD2A, VDD3A, VDD4A 4.7µF.µF pf pf pf pf VGGA, VGG2A, VGG3A, VGG4A 4.7µF.µF pf pf pf pf VGGA VDDA VGG2A VDD2A VGG3A VDD3A VGG4A VDD4A ADMV77 RFOUT 2 RFOUT 3 RFIN 2 RFIN VGGB VDDB VGG2B VDD2B VGG3B VDD3B VGG4B VDD4B VDET VREF pf pf pf pf VGGB, VGG2B, VGG3B, VGG4B 4.7µF.µF + kω kω V V OUT = V REF V DET VDDB, VDD2B, VDD3B, VDD4B 4.7µF +.µf pf pf pf pf kω kω kω kω +V +V SUGGESTED INTERFACE CIRCUIT Figure 47. Typical Application Circuit Rev. A Page of 8

16 ADMV77 Data Sheet ASSEMBLY DIAGRAM.µF.µF pf pf pf pf pf pf pf pf VGGA VDDA VGG2A VDD2A VGG3A VDD3A VGG4A VDD4A 3mil WIDE GOLD RIBBON (WEDGE BOND) 4.7µF Ω TRANSMISSION LINE 3 2 RFIN ADMV77 RFOUT 2 4.7µF 3mil WIDE GOLD RIBBON (WEDGE BOND) 6mil NOMINAL GAP VGGB VDDB VGG2B VDD2B VGG3B VDD3B VGG4B VDD4B VDET VREF pf pf pf pf pf pf pf pf.µf.µf Figure 48. Assembly Diagram Rev. A Page 6 of 8

17 Data Sheet ADMV77 MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane eutectically or with conductive epoxy. To bring RF to and from the chip, use Ω microstrip transmission lines on.27 mm ( mil) thick alumina thin film substrates (see Figure 49)..mm (.2") THICK GaAs MMIC.76mm (.3") RIBBON BOND RF GROUND PLANE.27mm (.") THICK ALUMINA THIN FILM SUBSTRATE Figure 49. Routing RF Signals To minimize bond wire length, place microstrip substrates as close to the die as possible. Typical die to substrate spacing is.76 mm to.2 mm (3 mil to 6 mil). HANDLING PRECAUTIONS To avoid permanent damage, adhere to the following precautions. Storage All bare die ship in either waffle or gel-based ESD protective containers, sealed in an ESD protective bag. After opening the sealed ESD protective bag, all die must be stored in a dry nitrogen environment. Cleanliness Handle the chips in a clean environment. Never use liquid cleaning systems to clean the chip. Static Sensitivity Follow ESD precautions to protect against ESD strikes Transients Suppress instrument and bias supply transients while bias is applied. To minimize inductive pickup, use shielded signal and bias cables. General Handling Handle the chip on the edges only using a vacuum collet or with a sharp pair of bent tweezers. Because the surface of the chip has fragile air bridges, never touch the surface of the chip with a vacuum collet, tweezers, or fingers. MOUNTING The chip is back metallized and can be die mounted with gold/tin (AuSn) eutectic preforms or with electrically conductive epoxy. The mounting surface must be clean and flat. Eutectic Die Attach It is best to use an 8% Au/% Sn preform with a work surface temperature of C and a tool temperature of C. When hot 9% nitrogen/% hydrogen gas is applied, maintain tool tip temperature at 29 C. Do not expose the chip to a temperature greater than 3 C for more than sec. No more than 3 sec of scrubbing is required for attachment. Epoxy Die Attach ATROX 8HTV is recommended for die attachment. Apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after placing it into position. Cure the epoxy per the schedule provided by the manufacturer. WIRE BONDING RF bonds made with 3 mil. mil gold ribbon are recommended for the RF ports. These bonds must be thermosonically bonded with a force of 4 g to 6 g. DC bonds of mil (. mm) diameter, thermosonically bonded, are recommended. Create ball bonds with a force of 4 g to g and wedge bonds with a force of 8 g to g. Create all bonds with a nominal stage temperature of C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than 2 mil (.3 mm). Rev. A Page 7 of 8

18 ADMV77 Data Sheet OUTLINE DIMENSIONS M TOP VIEW (CIRCUIT SIDE) SIDE VIEW -4-7-A Figure. 4-Pad Bare Die [CHIP] (C-4-2) Dimensions shown in millimeters ORDERING GUIDE Model, 2 Temperature Range Package Description Package Option ADMV77CHIPS C to +8 C 4-Pad Bare Die [CHIP] C-4-2 ADMV77-SX C to +8 C 4-Pad Bare Die [CHIP] C-4-2 The ADMV77-SX consists of two pairs of the die in a gel pack for sample orders. 2 This is a gel pack option; contact Analog Devices, Inc., sales representatives for additional packaging options. 8 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D648--2/8(A) Rev. A Page 8 of 8