50 GHz to 95 GHz, GaAs, phemt, MMIC, Wideband Power Amplifier ADPA7001CHIPS

Transcription

1 FEATURES Gain:.5 db typical at 5 GHz to 7 GHz S11: db typical at 5 GHz to 7 GHz S: 19 db typical at 5 GHz to 7 GHz P1dB: 17 dbm typical at 5 GHz to 7 GHz PSAT: 1 dbm typical OIP3: 5 dbm typical at 7 GHz to 9 GHz Supply voltage: 3.5 V at 35 ma 5 Ω matched input/output Die size:.5 mm 3.3 mm.5 mm APPLICATIONS Test instrumentation Military and space Telecommunications infrastructure 5 GHz to 95 GHz, GaAs, phemt, MMIC, Wideband Power Amplifier 1 RFIN FUNCTIONAL BLOCK DIAGRAM V GG A V DD 1A V DD A V GG 3A V DD 3A V DD A RFOUT GENERAL DESCRIPTION The is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (phemt), monolithic microwave integrated circuit (MMIC), balanced medium power amplifier, with an integrated temperature compensated on-chip power detector that operates from 5 GHz to 95 GHz. In the lower band of 5 GHz to 7 GHz, the provides.5 db (typical) of gain, 5.5 dbm output third-order intercept (OIP3), and 17 dbm of output power for 1 db gain compression. In V GG B V DD 1B V DD B V GG 3B V DD 3B V DD B V REF V DET Figure 1. the upper band of 7 GHz to 9 GHz, the provides db (typical) of gain, 5 dbm output IP3, and 17.5 dbm of output power for 1 db gain compression. The requires 35 ma from a 3.5 V supply. The amplifier inputs/outputs are internally matched to 5 Ω, facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via one.7 mm (3 mil) ribbon bond of.7 mm (3 mil) minimal length Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... Specifications GHz to 7 GHz Frequency Range GHz to 9 GHz Frequency Range GHz to 95 GHz Frequency Range... Absolute Maximum Ratings... 5 Thermal Resistance... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... Interface Schematics...7 Typical Performance Characteristics... Theory of Operation Applications Information... Mounting and Bonding Techniques for Millimeterwave GaAs MMICs... Typical Application Circuit... Assembly Diagram Outline Dimensions... 1 Ordering Guide... 1 REVISION HISTORY 3/19 Rev. to Rev. A Changes to Figure... /1 Revision : Initial Version Rev. A Page of 1

3 SPECIFICATIONS 5 GHz TO 7 GHz FREQUENCY RANGE TDIE BOTTOM = 5 C, VDD = VDD1A = VDDA = VDD3A = VDDA = 3.5 V and supply current (IDQ) = IDQ1A + IDQA + IDQ3A + IDQA = 35 ma, unless otherwise noted. Adjust VGG = VGGA = VGG3A from 1.5 V to V to achieve the desired IDQ. Typical VGG =.5 V for IDQ = 35 ma. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 5 7 GHz GAIN.5.5 db Gain Variation over Temperature. db/ C RETURN LOSS Input S11 db Output S 19 db OUTPUT Output Power for 1 db Compression P1dB dbm Saturated Output Power PSAT 1 dbm Output Third-Order Intercept OIP3 5.5 dbm Output power (POUT) per tone = dbm with 1 MHz tone spacing INPUT Input Third-Order Intercept IIP dbm POUT per tone = dbm with 1 MHz tone spacing SUPPLY Current IDQ 35 ma Adjust VGG to achieve IDQ = 35 ma typical Voltage VDD V 7 GHz TO 9 GHz FREQUENCY RANGE TDIE BOTTOM = 5 C, VDD = VDD1A = VDDA = VDD3A = VDDA = 3.5 V and IDQ = IDQ1A + IDQA + IDQ3A + IDQA = 35 ma, unless otherwise noted. Adjust VGG = VGGA = VGG3A from 1.5 V to V to achieve the desired IDQ. Typical VGG =.5 V for IDQ = 35 ma. Table. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 7 9 GHz GAIN db Gain Variation over Temperature. db/ C RETURN LOSS Input S11 1 db Output S 13 db OUTPUT Output Power for 1 db Compression P1dB 17.5 dbm Saturated Output Power PSAT 1 dbm Output Third-Order Intercept OIP3 5 dbm POUT per tone = dbm with 1 MHz tone spacing INPUT Input Third-Order Intercept IIP3 11 dbm POUT per tone = dbm with 1 MHz tone spacing SUPPLY Current IDQ 35 ma Adjust VGG to achieve IDQ = 35 ma typical Voltage VDD V Rev. A Page 3 of 1

4 9 GHz TO 95 GHz FREQUENCY RANGE TDIE BOTTOM = 5 C, VDD = VDD1A = VDDA = VDD3A = VDDA = 3.5 V, and IDQ = IDQ1A + IDQA + IDQ3A + IDQA = 35 ma, unless otherwise noted. Adjust VGG = VGGA = VGG3A from 1.5 V to V to achieve the desired IDQ. Typical VGG =.5 V for IDQ = 35 ma. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 9 95 GHz GAIN 15 db Gain Variation over Temperature. db/ C RETURN LOSS Input S11 15 db Output S db SUPPLY Current IDQ 35 ma Adjust VGG to achieve IDQ = 35 ma typical Voltage VDD V Rev. A Page of 1

5 ABSOLUTE MAXIMUM RATINGS Table. Parameter Drain Bias Voltage (VDD) Gate Bias Voltage (VGG) Radio Frequency (RF) Input Power (RFIN) Continuous Power Dissipation (PDISS), at TDIE BOTTOM = 5 C (Derate.95 mw/ C Above 5 C) Storage Temperature Range (Ambient) Operating Temperature Range (Die Bottom) ESD Sensitivity Human Body Model (HBM) Channel Temperature to Maintain 1 Million Hour Mean Time to Failure (MTTF) Nominal Channel Temperature at TDIE BOTTOM = 5 C, VDD = 3.5 V Rating.5 V V to V dc 17 dbm. W 5 C to +15 C 55 C to +5 C Class 5 V 175 C 13. C THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θjc is the junction-to-case thermal resistance Table 5. Thermal Resistance Package Type θjc Unit C C/W ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A Page 5 of 1

6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V GG A V DD 1A V DD A V GG 3A V DD 3A V DD A RFOUT 1 RFIN V GG B V DD 1B V DD B V GG 3B V DD 3B V DD B V REF V DET Figure. Pad Configuration 95- Table. Pad Function Descriptions Pad No. Mnemonic Description 1 RFIN RF Input. This pad is ac-coupled and matched to 5 Ω. See Figure 3 for the interface schematic. VGGA Gate Control Pad for the First and Second Stage Amplifiers. See Figure for the interface schematic. 3, VDD1A, VDDA Drain Bias Voltage Pads for the First and Second Stage Amplifiers. External bypass capacitors of pf,.1 µf, and.7 µf are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. 5 VGG3A Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure for the interface schematic., 7 VDD3A, VDDA Drain Bias Voltage Pads for the Third and Fourth Stage Amplifiers. External bypass capacitors of pf,.1 µf, and.7 µf are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. RFOUT RF Output. This pad is ac-coupled and matched to 5 Ω. See Figure 9 for the interface schematic. 9 VDET DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through an external resistor. See Figure 9 for the interface schematic. VREF DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature compensation of VDET. See Figure for the interface schematic. 11, VDDB, VDD3B Drain Bias Voltage Pads for the Fourth and Third Stage Alternative Bias Configuration. External bypass capacitors of pf,.1 µf, and.7 µf are required. See Figure 7 for the interface schematic. 13 VGG3B Gate Control Pad for the Third and Fourth Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure for the interface schematic., 15 VDDB, VDD1B Drain Bias Voltage Pads for the Second and First Stage Alternative Bias Configuration. External bypass capacitors of pf,.1 µf, and.7 µf are required. See Figure 7 for the interface schematic. VGGB Gate Control Pad for the First and Second Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF/dc ground. See Figure for the interface schematic. Rev. A Page of 1

7 INTERFACE SCHEMATICS RFIN 95-3 V DD 1B TO V DD B 95-7 Figure 3. RFIN Interface Schematic Figure 7. VDD1B to VDDB Interface Schematic V GG A V GG 3A 95- V GG B V GG 3B 95- Figure. VGGA and VGG3A Interface Schematic Figure. VGGB and VGG3B Interface Schematic V DD 1A TO V DD A RFOUT Figure 5. VDD1A to VDDA Interface Schematic 95-5 V DET Figure 9. RFOUT and VDET Interface Schematic 95-9 GND 95- Figure. GND Interface Schematic V REF Figure. VREF Interface Schematic 95- Rev. A Page 7 of 1

8 TYPICAL PERFORMANCE CHARACTERISTICS BROADBAND GAIN AND RETURN LOSS (db) S11 S1 S GAIN (db) 1 1.5V.V.5V 3.V 3.5V.V Figure 11. Broadband Gain and Return Loss vs. Frequency Figure. Gain vs. Frequency for Various VDD Values GAIN (db) 1 +5 C +5 C 55 C INPUT RETURN LOSS (db) C +5 C 55 C Figure. Gain vs. Frequency for Various Temperatures Figure 15. Input Return Loss vs. Frequency at Various Temperatures GAIN (db) 1 ma 5mA 3mA 35mA ma 5mA INPUT RETURN LOSS (db) ma 5mA 3mA 35mA ma 5mA Figure 13. Gain vs. Frequency for Various IDQ Values Figure. Input Return Loss vs. Frequency for Various IDQ Values 95- Rev. A Page of 1

9 INPUT RETURN LOSS (db) V.V.5V 3.V 3.5V.V OUTPUT RETURN LOSS (db) V.V.5V 3.V 3.5V.V Figure 17. Input Return Loss vs. Frequency for Various VDD Values Figure. Output Return Loss vs. Frequency for Various VDD Values 95- OUTPUT RETURN LOSS (db) C +5 C 55 C OUTPUT RETURN LOSS (db) ma 5mA 3mA 35mA ma 5mA Figure 1. Output Return Loss vs. Frequency at Various Temperatures Figure 1. Output Return Loss vs. Frequency for Various IDQ Values P1dB (dbm) P SAT (dbm) +5 C +5 C 55 C +5 C +5 C 55 C Figure 19. P1dB vs. Frequency at Various Temperatures Figure. PSAT vs. Frequency at Various Temperatures Rev. A Page 9 of 1

10 1 1 P1dB (dbm) ma 5mA 3mA 35mA ma 5mA P SAT (dbm) ma 5mA 3mA 35mA ma 5mA Figure 3. P1dB vs. Frequency for Various IDQ Values Figure. PSAT vs. Frequency for Various IDQ Values 1 1 P1dB (dbm) P SAT (dbm) 1.5V.V.5V 3.V 3.5V.V 1.5V.V.5V 3.V 3.5V.V Figure. P1dB vs. Frequency for Various VDD Values Figure 7. PSAT vs. Frequency for Various VDD Values IIP3 (dbm) +5 C +5 C 55 C IIP3 (dbm) ma 5mA 3mA 35mA ma 5mA Figure 5. IIP3 vs. Frequency at Various Temperatures Figure. IIP3 vs. Frequency for Various IDQ Values Rev. A Page of 1

11 9 7 5 IIP3 (dbm) 1.5V 3.V.V 3.5V.5V.V OIP3 (dbm) V.V.5V 3.V 3.5V.V Figure 9. IIP3 vs. Frequency for Various VDD Values Figure 3. OIP3 vs. Frequency for Various VDD Values 9 1. OIP3 (dbm) P DISS (W) GHz 55GHz GHz 5GHz 7GHz 75GHz GHz 5GHz GHz C +5 C 55 C INPUT POWER AT 5 C Figure 3. OIP3 vs. Frequency at Various Temperatures Figure 33. PDISS vs. Input Power at 5 C for Various Frequencies 9 OIP3 (dbm) ma 5mA 3mA 35mA ma 5mA DRAIN SUPPLY CURRENT (ma) 3 3 5GHz 55GHz GHz 5GHz 7GHz 75GHz GHz 5GHz GHz Figure 31. OIP3 vs. Frequency for Various IDQ Values RF INPUT POWER (dbm) Figure 3. Drain Supply Current vs. RF Input Power for Various Frequencies 95-3 Rev. A Page 11 of 1

12 REVERSE ISOLATION (db) C +5 C 55 C GATE SUPPLY CURRENT (ma) GHz 55GHz GHz 5GHz 7GHz 75GHz GHz 5GHz GHz RF INPUT POWER (dbm) Figure 35. Reverse Isolation vs. Frequency at Various Temperatures Figure 37. Gate Supply Current vs. RF Input Power V REF V DET (V) C +5 C 55 C.1 1 OUTPUT POWER (dbm) 95-3 DRAIN SUPPLY CURRENT (ma) GATE SUPPLY VOLTAGE (V) Figure 3. Detector Voltage (VREF VDET) vs. Output Power for Various Temperatures at 7 GHz Figure 3. Drain Supply Current vs. Gate Supply Voltage Rev. A Page of 1

13 THEORY OF OPERATION The architecture of the medium power amplifier is shown in Figure 39. The uses four cascaded, four-stage amplifiers operating in quadrature between six 9 hybrids. The input signal is divided evenly into two. Then, each signal is again divided into two, and each of these paths is amplified through four independent gain stages. Then, the amplified signals are combined at the output. This balanced amplifier approach forms an amplifier with a combined gain of db and a PSAT value of 1 dbm. A portion of the RF output signal is directionally coupled to a diode for detection of the RF output power. When the diode is dc biased, it rectifies the RF power and makes it available for measurement as a dc voltage at VDET. To allow temperature compensation of VDET, an identical and symmetrically located circuit, minus the coupled RF power, is available via VREF. Taking the difference of VREF VDET provides a temperature compensated signal that is proportional to the RF output. (see Figure 3). The 9 hybrids ensure that the input and output return losses are greater than or equal to 15 db and db, respectively. See the application circuits shown in Figure 3 and Figure for further details on biasing the various blocks. 9 COUPLER FOUR STAGE BALANCED AMPLIFIER 9 COUPLER 9 COUPLER 9 COUPLER RFOUT RFIN 9 COUPLER FOUR STAGE BALANCED AMPLIFIER 9 COUPLER DIRECTIONAL COUPLER Figure 39. Architecture V REF V DET Rev. A Page 13 of 1

14 APPLICATIONS INFORMATION The is a GaAs, phemt, MMIC power amplifier. Capacitive bypassing is required for VDD1A through VDDA and VDD1B through VDDB (see Figure 3). VGGA is the gate bias pad for the first and second gain stages. VGG3A is the gate bias pad for the third and fourth gain stages. Apply a gate bias voltage to VGGA and VGG3A, and use capacitive bypassing as shown in Figure 3. All measurements for this device were taken using the typical application circuit (see Figure 3) and configured as shown in the assembly diagram (Figure 5). The following is the recommended bias sequence during power-up: 1. Connect GND to RF/dc ground.. Set the gate bias voltage to 1.5 V. 3. Set all the drain bias voltages, VDD = 3.5 V.. Increase the gate bias voltage to achieve a quiescent current, IDQ = 35 ma. 5. Apply the RF signal. The following is the recommended bias sequence during power-down: 1. Turn off the RF signal.. Decrease the gate bias voltage to 1.5 V to achieve IDQ = ma (approximately). 3. Decrease all of the drain bias voltages to V.. Increase the gate bias voltage to V. RFIN V GG A V GG B V DD 1A V DD 1B V DD A V DD B V DD 3A V DD 3B V DD A V DD B RFOUT Table 7. Power Selection Table 1, IDQ (ma) Gain (db) P1dB (dbm) OIP3 (dbm) PDISS (mw) VGG (V) Data taken at the following nominal bias conditions: VDD = 3.5 V, T = 5 C. Adjust VGGA and VGG3A from 1.5 V to V to achieve the desired drain current. The VDD = 3.5 V and IDD = 35 ma bias conditions are recommended to optimize overall performance. Unless otherwise noted, the data shown was taken using the recommended bias conditions. Operation of the at different bias conditions may provide performance that differs from what is shown in Table 1 and Table. Biasing the for higher drain current typically results in higher P1dB, output IP3, and gain at the expense of increased power consumption (see Table 7). MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane with conductive epoxy (see the Handling Precautions section, the Mounting section, and the Wire Bonding section). Microstrip, 5 Ω transmission lines on.7 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip. Raise the die.75 mm (3 mil) to ensure that the surface of the die is coplanar with the surface of the substrate. Place microstrip substrates as close to the die as possible to minimize ribbon bond length. Typical die to substrate spacing is.7 mm to.15 mm (3 mil to mil). To ensure wideband matching, a 15 ff capacitive stub is recommended on the PCB board before the ribbon bond. V GG 3A V GG 3B Figure. Simplified Block Diagram Simplified bias pad connections to dedicated gain stages and dependence and independence among pads are shown in Figure MATCHING STUB/BOND PAD SHUNT CAPACITANCE = 15fF 5Ω TRANSMISSION LINE 3mil GOLD RIBBON RFIN PCB BOARD Rev. A Page of 1 3mil GAP MMIC Figure 1. High Frequency Input Wideband Matching 95-

15 RFOUT 3mil GOLD RIBBON MATCHING STUB/BOND PAD SHUNT CAPACITANCE = 15fF 5Ω TRANSMISSION LINE Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems. Follow ESD precautions to protect against ESD strikes. While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pickup. Handle the chip along the edges with a vacuum collet or with a sharp pair of tweezers. The surface of the chip have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. MMIC 3mil GAP PCB BOARD Figure. High Frequency Output Wideband Matching Place microstrip substrates as close to the die as possible to minimize bond wire length. Typical die to substrate spacing is.7 mm to.15 mm (3 mil to mil). Handling Precautions To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. After the sealed ESD protective bag is opened, store all die in a dry nitrogen environment Mounting Before epoxy die is attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after it is placed into position. Cure the epoxy per the schedule of the manufacturer. Wire Bonding RF bonds made with.3 in..5 in. gold ribbon are recommended for the RF ports. These bonds must be thermosonically bonded with a force of g to g. DC bonds of.1 in. (.5 mm) diameter, thermosonically bonded, are recommended. Create ball bonds with a force of g to 5 g and wedge bonds with a force of 1 g to g. Create all bonds with a nominal stage temperature of 15 C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than mil (.31 mm). Alternatively, short ( 3 mil) RF bonds made with two 1 mil wires can be used. Rev. A Page 15 of 1

16 TYPICAL APPLICATION CIRCUIT The drain and gate voltages can be applied to either the north or the south side of the circuit. NO DC BIAS APPLIED NC +.7µF.1µF pf pf pf pf NC +.7µF.1µF pf pf V GG B TO V GG 3B RFIN 1.7µF.1µF pf pf 11 9 V DET V REF RFOUT kω +5V kω kω kω kω +5V V OUT = V REF V DET V DD 1B TO V DD B +.7µF.1µF pf pfpfpf Figure 3. Application Circuit kω 5V SUGGESTED CIRCUIT 95-3 V DD 1A TO V DD A +.7µF.1µF pf pf pf pf V GG A TO V GG 3A +.7µF.1µF pf pf RFIN V DET V REF RFOUT kω +5V kω kω kω +5V NC NC +.7µF.1µF pf +.7µF.1µF pf pfpfpf NO DC BIAS APPLIED pf kω kω Figure. Alternate Application Circuit 5V SUGGESTED CIRCUIT V OUT = V REF V DET 95- Rev. A Page of 1

17 ASSEMBLY DIAGRAM Figure 5. Assembly Diagram 95- Rev. A Page 17 of 1

18 OUTLINE DIMENSIONS TOP VIEW (CIRCUIT SIDE) *AIR BRIDGE AREA *This die utilizes fragile air bridges. Any pickup tools used must not contact this area. Figure. -Pad Bare Die [CHIP] (C--) Dimensions shown in millimeters SIDE VIEW ORDERING GUIDE Model Temperature Range Package Description Package Option 55 C to +5 C -Pad Bare Die [CHIP] C-- -SX 55 C to +5 C -Pad Bare Die [CHIP] C A 1 19 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D95--3/19(A) Rev. A Page 1 of 1