DG200, DG201. CMOS Dual/Quad SPST Analog Switches. Description. Features. Ordering Information. Applications. Pinouts.

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1 SEMICONDUCTOR DG200, DG20 December 993 CMOS Dual/Quad SPST Analog Switches Features Switches Greater than 28V P-P Signals with ±5 Supplies Break-Before-Make Switching t OFF 250ns, t ON 700ns Typical TTL, DTL, CMOS, PMOS Compatible Non-Latching with Supply Turn-Off Complete Monolithic Construction Industry Standard (DG200, DG20) Applications Data Acquisition Sample and Hold Circuits Operational Amplifier Gain Switching Networks Description The DG200 and DG20 solid state analog gates are designed using an improved, high voltage CMOS monolithic technology. They provide ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates has been eliminated by Harris's CMOS technology. The DG200 and DG20 are completely specification and pinout compatible with the industry standard devices. Ordering Information PART NUMBER TEMPERATURE PACKAGE DG200AA -55 o C to +25 o C 0 Pin Metal Can DG200AK -55 o C to +25 o C 4 Lead Ceramic DIP DG200BA -25 o C to +85 o C 0 Pin Metal Can DG200BK -25 o C to +85 o C 4 Lead Ceramic DIP DG200CJ 0 o C to +70 o C 4 Lead Plastic DIP DG200AA/883B -55 o C to +25 o C 0 Pin Metal Can DG200AK/883B -55 o C to +25 o C 4 Lead Ceramic DIP DG20AK -55 o C to +25 o C 6 Lead Ceramic DIP DG20BK -25 o C to +85 o C 6 Lead Ceramic DIP DG20CJ 0 o C to +70 o C 6 Lead Plastic DIP DG20AK/883B -55 o C to +25 o C 6 Lead Ceramic DIP Pinouts DG200 (CDIP, PDIP) TOP VIEW DG200 (TO-00 METAL CAN) TOP VIEW DG20 (CDIP, PDIP) TOP VIEW IN 2 NC GND NC S IN 3 NC 2 V+ (SUBSTRATE) NC 0 S 9 D V+ (SUBSTRATE AND CASE) IN 2 2 GND IN 3 S S 8 7 D IN D S GND S 4 D IN 2 S 2 V+(SUBSTRATE) S 3 D IN IN 3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright Harris Corporation File Number 35

2 Schematic Diagram ( / 2 DG200, / 4 DG20) DG200, DG20 V+ Q3 Q7 Q5 Q4 Q8 Q5 Q Q0 V+ Q2 Q3 GATE PROTECTION RESISTOR Q2 Q9 S Q D Q4 Q6 INPUT Functional Diagram S IN N P D DG200, DG20 SWITCH CELL 9-4

3 Absolute Maximum Ratings V+, <36V V+ - V D <30V V D <30V V D - V S <28V V IN - GND <20V Storage Temperature Range o C to +50 o C Lead Temperature (Soldering 0s) o C Specifications DG200 Thermal Information Thermal Resistance θ JA θ JC Ceramic DIP Package o C/W 24 o C/W Plastic DIP Package o C/W - Metal Can Package o C/W 65 o C/W Operating Temperature Range A Suffix o C to +25 o C B Suffix o C to +85 o C C Suffix o C to +70 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (T A = +25 o C, V+ = +5V, = -5V) MILITARY COMMERCIAL / INDUSTRIAL PARAMETER TEST CONDITIONS -55 o C +25 o C +25 o C 0 o C TO -25 o C +25 o C +70 o C TO +85 o C UNITS Input Logic Current, V IN = 0.8V (Notes 2, 3) ±0 ± ±0 - ±0 ±0 µa I IN(ON) Input Logic Current, V IN = 2.4V (Notes 2, 3) ±0 ± ±0 - ±0 ±0 µa I N(OFF) Drain-Source On Resistance, r DS(ON) I S = 0mA, V ANALOG = ±0V Ω Channel-to-Channel - 25 (Typ) (Typ) - Ω r DS(ON) Match, r DS(ON) Minimum Analog Signal Handling Capability, V ANALOG - ±5V - - ±5V - V Switch OFF Leakage V ANALOG = -4V to +4V - ± ±5 00 na Current, I D(OFF) Switch OFF Leakage V ANALOG = -4V to +4V - ± ±5 00 na Current, I S(OFF) Switch ON Leakage Current, V D = V S = -4V to +4V - ± ±0 200 na I D(ON) + I S(ON) Switch ON Time R L = kω, V ANALOG = (Note ), t ON -0V to +0V (Figure 5) Switch OFF Time, t OFF R L = kω, V ANALOG = -0V to +0V (Figure 5) µs µs Charge Injection, Q (INJ.) Figure 6-5 (Typ) (Typ) - mv Minimum Off Isolation Rejection Ratio, OIRR f = MHz, R L = 00Ω, C L 5pF (Figure 7, Note ) - 54 (Typ) (Typ) - db +Power Supply V IN = 0V or V IN = 5V µa Quiescent Current, I V -Power Supply µa Quiescent Current, I V2 Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR One Channel Off - 54 (Typ) (Typ) - db NOTES:. Pull Down Resistor must be 2kΩ. 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high logic inputs and all channels are turned on by low 0 inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -20µA. 9-5

4 Absolute Maximum Ratings V+ to <36V V+ to V D <30V V D to <30V V D to V S <28V to <33V to V IN <30V to GND <20V V IN to GND <20V Current (Any Terminal) <30mA Storage Temperature Range o C to +50 o C Lead Temperature (Soldering 0s) o C Specifications DG20 Thermal Information Thermal Resistance θ JA θ JC Ceramic DIP Package o C/W 24 o C/W Plastic DIP Package o C/W - Operating Temperature Range A Suffix o C to +25 o C B Suffix o C to +85 o C C Suffix o C to +70 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (T A = +25 o C, V+ = +5V, = -5V) MILITARY COMMERCIAL / INDUSTRIAL PARAMETER TEST CONDITIONS -55 o C +25 o C +25 o C 0 o C TO -25 o C +25 o C +70 o C TO +85 o C UNITS Input Logic Current, V IN = 0.8V (Note ) 0 ± 0 ± ± 0 µa I IN(ON) Input Logic Current, V IN = 2.4V (Note ) 0 ± 0 ± ± 0 µa I N(OFF) Drain-Source On Resistance, r DS(ON) I S = 0mA, V ANALOG = ±0V Ω Channel-to-Channel - 25 (Typ) (Typ) - Ω r DS(ON) Match, r DS(ON) Minimum Analog Signal Handling Capability, V ANALOG - ±5 (Typ) - - ±5 (Typ) - V Switch OFF Leakage V ANALOG = -4V to +4V - ± 00 - ±5 00 na Current, I D(OFF) Switch OFF Leakage V ANALOG = -4V to +4V - ± 00 - ±5 00 na Current, I S(OFF) Switch ON Leakage Current, V D = V S = -4V to +4V - ± ±5 200 na I D(ON) + I S(ON) Switch ON Time R L = kω, V ANALOG = (Note 2), t ON -0V to +0V (Figure 5) Switch OFF Time R L = kω, V ANALOG = (Note 2), t OFF -0V to +0V (Figure 5) µs µs Charge Injection, Q (INJ.) Figure 6-5 (Typ) (Typ) - mv Minimum Off Isolation Rejection Ratio, OIRR f = MHz, R L = 00Ω, C L 5pF, (Figure 7) - 54 (Typ) (Typ) - db +Power Supply V IN = 0V or V IN = 5V µa Quiescent Current, I+ Q -Power Supply µa Quiescent Current, I- Q Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR One Channel Off - 54 (Typ) (Typ) - db NOTES:. Typical values are for design aid only, not guaranteed and not subject to production testing. 2. All channels are turned off by high logic inputs and all channels are turned on by low 0 inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -20µA. 9-6

5 DG200, DG20 Performance Curves DRAIN SOURCE ON RESISTANCE (Ω) o C +25 o C -55 o C V+ = +5V = -5V DRAIN VOLTAGE (V) FIGURE. R DS(ON) vs V D AND TEMPERATURE DRAIN SOURCE ON RESISTANCE (Ω) A: V+ = +5V, = -5V B: V+ = +2V, = -2V C: V+ = +0V, = -0V D: V+ = +8V, = -8V DRAIN VOLTAGE (V) FIGURE 2. r DS(ON) vs V D AND POWER SUPPLY VOLTAGE D C B A CHANNEL ON LEAKAGE CURRENT (na) TEMPERATURE ( o C) SOURCE OR DRAIN OFF LEAKAGE CURRENT (na) TEMPERATURE ( o C) FIGURE 3. I D(ON) vs TEMPERATURE FIGURE 4. I S(OFF) OR I D(OFF) vs TEMPERATURE Pin Description DG200 (4 LEAD DIP) PIN SYMBOL DESCRIPTION IN 2 Logic control for switch 2 2 NC No Connection 3 GND Ground Terminal (Logic Common) 4 NC No Connection 5 S 2 Source (input) terminal for switch 2 6 Drain (output) terminal for switch 2 7 Negative power supply terminal 8 Logic reference voltage 9 D Drain (output) terminal for switch 0 S Source (input) terminal for switch NC No Connection 2 V+ Positive power supply terminal (substrate) 3 NC No Connection 4 IN Source (input) terminal for switch DG20 (6 LEAD DIP) PIN SYMBOL DESCRIPTION IN Logic control for switch 2 D Drain (output) terminal for switch 3 S Source (input) terminal for switch 4 Negative power supply terminal 5 GND Ground terminal (Logic Common) 6 S 4 Source (input) terminal for switch 4 7 D 4 Drain (output) terminal for switch 4 8 IN 4 Logic control for switch 4 9 IN 3 Logic control for switch 3 0 D 3 Drain (output) terminal for switch 3 S 3 Source (input) terminal for switch 3 2 Logic reference voltage 3 V+ Positive power supply terminal (substrate) 4 S 2 Source (input) terminal for switch 2 5 Drain (output) terminal for switch 2 6 IN 2 Logic control for switch 2 9-7

6 DG200, DG20 Test Circuits ANALOG INPUT 0V 3V 0V LOGIC V OUT INPUT 3V 2kΩ 0pF kω 0V LOGIC INPUT NOTE: All channels are turned off by high logic inputs and all channels are turned on by low 0 inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -20µA. FIGURE 5. FIGURE 6. 0,000pF ANALOG INPUT 0V V OUT LOGIC INPUT * 2V P-P AT MHz 5Ω V OUT 00Ω * Pull Down Resistor must be 2kΩ. FIGURE 7. Typical Applications Using the Terminal The DG200 and DG20 have an internal voltage divider setting the TTL threshold on the input control lines for V+ equal to +5V. The schematic shown in Figure 8 with nominal resistor values, gives approximately 2.4V on the pin. As the TTL input signal goes from +0.8V to +2.4V, Q and Q2 switch states to turn the switch ON and OFF. V+ (+5V) If the power supply voltage is less than +5V, then a resistor must be added between V+ and the pin, to restore +2.4V at. The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. In general, the low logic level should be <0.8V to prevent Q and Q2 from both being ON together (this will cause incorrect switch function). TABLE. Q 3kΩ R EXT TTL RESISTOR CMOS RESISTOR V+ SUPPLY (V) (kω) (kω) kΩ (34) 34 GATE PROTECTION RESISTOR Q2 +8 (27) INPUT FIGURE

7 DG200 Metallization Topology DIE DIMENSIONS: 74 x 77 x 4 ± mils METALLIZATION: Type: Al Thickness: 0kÅ ± kå GLASSIVATION: Type: SiO 2 /Si 3 N 4 SiO 2 Thickness: 7kÅ ±.4kÅ Si 3 N 4 Thickness: 8kÅ ±.2kÅ WORST CASE CURRENT DENSITY: x 0 5 A/cm 2 Metallization Mask Layout DG200 D (9) (7) (6) S (0) (5) S 2 (SUBSTRATE)* (2) (4) () (3) IN IN 2 GND * Backside of Chip is V+ 9-9

8 DG20 Metallization Topology DIE DIMENSIONS: 94 x 0 x 4 ± mils METALLIZATION: Type: Al Thickness: 0kÅ ± kå GLASSIVATION: Type: SiO 2 /Si 3 N 4 SiO 2 Thickness: 7kÅ ±.4kÅ Si 3 N 4 Thickness: 8kÅ ±.2kÅ WORST CASE CURRENT DENSITY: x 0 5 A/cm 2 Metallization Mask Layout DG20 D (2) IN () IN 2 (6) (5) S (3) (4) S 2 (4) (3) V+ (SUBSTRATE)* GND (5) S 4 (6) () S 3 (7) (8) (9) (0) D 4 IN 4 IN 3 D 3 * Backside of Chip is V+ 9-20