DATASHEET EL1848. Features. Ordering Information. Applications. Typical Connection. White LED Step-Up Regulator. FN7427 Rev 0.

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1 DATASHEET E1 White ED Step-Up Regulator FN2 Rev 0.00 The E1 is a constant current boost regulator specially designed for driving white EDs. It can drive EDs in series or up to 9 EDs in parallel/series configuration and achieves efficiency up to 91%. Features 2.6V to 1.2V input voltage 1V maximum output voltage The brightness of the EDs is adjusted through a voltage level on the CNT pin. When the level falls below 0.1V, the chip goes into shut-down mode and consumes less than 1µA of supply current for less than 5.5V. Drives up to 9 EDs, in a series 1MHz switching frequency Up to 91% efficiency The E1 is available in -pin TSOT and MSOP packages. The TSOT is just 1mm high, compared to 1.5mm for the standard SOT-2 package. Ordering Information 1µA maximum shut-down current Dimming control -pin TSOT and MSOP packages Pb-free Available PART NUMBER PACKAGE TAPE & REE PKG. DWG. # Applications E1IWT-T -Pin TSOT (K pcs) MDP009 PDAs E1IWT-TA -Pin TSOT (250 pcs) MDP009 Cellular phones E1IWTZ-T (See Note) E1IWTZ- TA (See Note) -Pin TSOT (Pb-free) -Pin TSOT (Pb-free) (K pcs) MDP009 (250 pcs) MDP009 E1IY -Pin MSOP - MDP00 E1IY-T -Pin MSOP MDP00 E1IY-T1 -Pin MSOP 1 MDP00 Digital cameras White ED backlighting Typical Connection 2.6V TO 5.5V C 1.µF µh D C 2 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MS classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. V CTR VIN CNT X PGND R 1 5 C COMP SGND FN2 Rev 0.00 Page 1 of 12

2 Pinouts E1 (-PIN TSOT) TOP VIEW E1 (-PIN MSOP) TOP VIEW COMP 1 VIN 1 CNT CNT 2 VIN 2 COMP 6 SGND PGND 6 X X 5 PGND SGND 5 FN2 Rev 0.00 Page 2 of 12

3 Absolute Maximum Ratings (T A = 25 C) COMP, CNT, to SGND V to +6V to SGND V V OUT to SGND V X to PGND V SGND to PGND V to +0.V Storage Temperature C to +150 C Ambient Operating Temperature C to +5 C Power Dissipation See Curves Operating Junction Temperature C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. This part is ESD sensitive. Handle with care. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests areat the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications = V, V O = 12V, C 1 =.µf, = µh, C 2 =, C =, R 1 = 5, T A = 25 C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Input Voltage V I Q1 Total Input Current at Shut-down V CNT = 0V 1 µa I Q1 Quiescent Supply Current at V O Pin V CNT = 1V, load disconnected ma I COMP COMP Pin Pull-up Current COMP connected to SGND µa V COMP COMP Voltage Swing V I CNT CNT Shut-down Current CNT = 0V 1 µa V CNT1 Chip Enable Voltage 20 mv V CNT2 Chip Disable Voltage 100 mv I OUT_ACCURACY V CNT = 1V V CNT = 1V ma V OUT1 Over-voltage Threshold V OUT rising V V OUT2 Over-voltage Threshold V OUT falling, with resistive load V IX MOSFET Current imit 00 ma R DS_ON MOSFET On-resistance 0. I EAK MOSFET eakage Current V CNT = 0V, V X = 12V 1 µa F S Switching Frequency khz D MAX Maximum Duty Ratio V CNT = 2V, I S = % I Input Bias Current 1 µa I O / ine Regulation = 2.6V - 5.5V 0.0 %/V Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 COMP Compensation pin. A compensation cap (00pF to ) is normally connected between this pin and SGND. 2 CNT Control pin for dimming and shut-down. A voltage between 250mV and 5.5V controls the brightness, and less than 100mV shuts down the converter. Output voltage sense. Use for over voltage protection. X Inductor connection pin. The drain of internal MOSFET. 5 PGND Power Ground pin. The source of internal MOSFET. 6 SGND Signal Ground. Ground pin for internal control circuitry. Needs to connect to PGND at only one point. Current sense pin. Connect to sensing resistor to set the ED bias current. VIN Power supply for internal control circuitry. FN2 Rev 0.00 Page of 12

4 Block Diagram 2.6V TO 5.5V C IN.µF REFERENCE GENERATOR 1MHz OSCIATOR THERMA SHUTDOWN OVER-VOTAGE PROTECTION V OUT µh X C COMP COMP + BOOST I-SENSE PWM OGIC I(ED) C OUT PWM SIGNA V CNT CNT 61K START-UP CONTRO ERROR AMP + - PGND C S 5 50K SGND Typical Performance Curves All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a series; unless otherwise specified V CNT =0V, 0.1V WHITE EDs DISCONNECTED F S (MHz) I IN (µa) (V) (V) FIGURE 1. SWITCHING FREQUENCY vs FIGURE 2. QUIESCENT CURRENT FN2 Rev 0.00 Page of 12

5 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a series; unless otherwise specified. I ED (ma) V CNT (V) FIGURE. I ED vs V CNT I ED (ma) V CNT =1V (V) FIGURE. I ED vs.µf µh BAT5HT1 2 EDs IN A SERIES 90 =.2V 5 V CTR VIN X 2 5 CNT PGND 1 6 COMP SGND =2.V =COICRAFT PO10-CM FIGURE 5A. 2 EDs IN A SERIES FIGURE 5. FIGURE 5B. EFFICIENCY vs I O.µF µh BAT5HT1 EDs IN A SERIES 90 V CTR VIN X 2 5 CNT PGND 1 6 COMP SGND =.2V =2.V =COICRAFT PO10-CM FIGURE 6A. EDs IN A SERIES FIGURE 6. FIGURE 6B. EFFICIENCY vs I O FN2 Rev 0.00 Page 5 of 12

6 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a series; unless otherwise specified..µf µh BAT5HT1 2 EGS OF 2 EDs IN A SERIES 90 =.2V 5 VIN X 5 5 V CTR 2 5 CNT PGND 1 6 COMP SGND 0 5 =2.V =COICRAFT PO10-CM FIGURE A. 2 EGS OF 2 EDs IN A SERIES FIGURE. FIGURE B. EFFICIENCY vs I O.µF µh BAT5HT1 2 EGS OF EDs IN A SERIES 90 =.2V VIN X 5 5 V 2 5 CTR CNT PGND 1 6 COMP SGND =2.V =SUMIDA CMD1D1-µH FIGURE A. 2 EGS OF EDs IN A SERIES FIGURE. FIGURE B. EFFICIENCY vs I O.µF 15µH BAT5HT1 EGS OF 2 EDs IN A SERIES =.2V VIN X V CTR CNT PGND 1 6 COMP SGND =2.V =SUMIDA CMD1D1-15µH FIGURE 9A. EGS OF 2 EDs IN A SERIES FIGURE 9. FIGURE 9B. EFFICIENCY vs I O FN2 Rev 0.00 Page 6 of 12

7 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a series; unless otherwise specified..µf 15µH BAT5HT1 EGS OF EDs IN A SERIES =.2V VIN X V CTR CNT PGND 1 6 COMP SGND =2.V =SUMIDA CMD1D1-15µH FIGURE 10A. EGS OF EDs IN A SERIES FIGURE 10. FIGURE 10B. EFFICIENCY vs I O JEDEC JESD51- HIGH EFFECTIVE THERMA CONDUCTIVITY TEST BOARD 1 JEDEC JESD51- OW EFFECTIVE THERMA CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) mW MSOP/10 JA =115 C/W POWER DISSIPATION (W) 0.5 6mW MSOP/10 JA =206 C/W AMBIENT TEMPERATURE ( C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN2 Rev 0.00 Page of 12

8 Waveforms All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a series; unless otherwise specified. C =00pF I IN 50mA/DIV 2V/DIV I IN 50mA/DIV V CNT 1V/DIV V CNT 1V/DIV I ED 10mA/DIV I ED 10mA/DIV 10ms/DIV FIGURE 1. START-UP 0.1ms/DIV FIGURE 1. SHUT-DOWN I ED =15mA V CNT 2V 1V 10mV/DIV V O 1.2V 12.9V I 100mA/DIV 0mA V X 10V/DIV I ED 15mA V O 50mV/DIV 20ms/DIV FIGURE 15. TRANSIENT RESPONSE 1µs/DIV FIGURE 16. CONTINUOUS CONDUCTION MODE V CTR =0.V, I ED =5mA 10mV/DIV V O (5V/DIV) I 100mA/DIV V X 10V/DIV V COMP (1V/DIV) V O 50mV/DIV 1µs/DIV FIGURE 1. DISCONTINUOUS CONDUCTION MODE FIGURE 1. OVER VOTAGE PROTECTION (ED DISCONNECTED) FN2 Rev 0.00 Page of 12

9 Detailed Description The E1 is a constant current boost regulator specially designed for driving white EDs. It can drive up to EDs in series or 9 EDs in parallel/series configuration and achieves efficiency up to 91%. The brightness of the EDs is adjusted through a voltage level on the CNT pin. When the level falls below 0.1V, the chip goes into shut-down mode and consumes less than 1µA of current for less than 5.5V. Steady-State Operation E1 is operated in constant frequency PWM. The switching is around 1MHz. Depending on the input voltage, the inductance, the type of EDs driven, and the ED s current, the converter operates at either continuous conduction mode or discontinuous conduction mode (see waveforms). Both are normal. Brightness Control ED s current is controlled by the voltage level on CNT pin (V CNT ). This voltage can be either a DC or a PWM signal with frequency less than 200Hz (for C =00pF). When a higher frequency PWM is used, an RC filter is recommended before the CNT pin (see Figure 1). hiccough continues until ED is applied or converter is shut down. When designing the converter, caution should be taken to ensure the highest operating ED voltage does not exceed 1V, the minimum shut-down voltage. There is no external component required for this function. Component Selection The input and output capacitors are not very important for the converter to operate normally. The input capacitance is normally 0.22µF -.µf and output capacitance 0.22µF -. Higher capacitance is allowed to reduce the voltage/current ripple, but at added cost. Use X5R or XR type (for its good temperature characteristics) of ceramic capacitors with correct voltage rating and maximum height. When choosing an inductor, make sure the inductor can handle the average and peak currents giving by following formulas (0% efficiency assumed): I O V O I AVG = I PK = I AVG + -- I 2 V O I = V O F S PWM SIGNA 100K CNT COMP FIGURE 19. PWM BRIGHTNESS CONTRO The relationship between the ED current and CNT voltage level is as follows: V CNT I ED = R 1 When R 1 is 5, 1V of V CNT conveniently sets I ED to 15mA. The range of V CNT is 250mV to 5.5V. Shut-Down When V CNT is less than 100mV, the converter is in shut-down mode. The max current consumed by the chip is less than 1µA for less than 5.5V. Over-Voltage Protection When an ED string is disconnected from the output, V O will continue to rise because of no current feedback. When V O reaches 1V (nominal), the chip will shut down. The output voltage will drop. When V O drops below 11V (nominal), the chip will boost output voltage again until it reaches 1V. This where: I is the peak-to-peak inductor current ripple in Ampere inductance in µh FS switching frequency, typical 1MHz A wide range of inductance (6.µH - 6µH) can be used for the converter to function correctly. For the same series of inductors, the lower inductance has lower DC resistance (DCR), which has less conducting loss. But the ripple current is bigger, which generates more RMS current loss. Figure 9 shows the efficiency of the demo board under different inductance for a specific series of inductor. For optimal efficiency in an application, it is a good exercise to check several adjacent inductance values of your preferred series of inductors. FN2 Rev 0.00 Page 9 of 12

10 For the same inductance, higher overall efficiency can be obtained by using lower DCR inductor. EFFICIENCY vs I O 5 =.V FOR DIFFERENT 1 =µh =22µH =15µH =10µH 9 =Coilcraft PO10 SERIES 1mm HEIGHT The demo board is a good example of layout based on the principle. Please refer to the E1 Application Brief for the layout. FIGURE 20. EFFICIENCY OF DIFFERENT INDUCTANCE ( EDs IN A SERIES) The diode should be Schottky type with minimum reverse voltage of 20V. The diode's peak current is the same as inductor's peak current, the average current is I O, and RMS current is: I DRMS = I AVG I O Ensure the diode's ratings exceed these current requirements. White ED Connections One leg of EDs connected in series will ensure the uniformity of the brightness. 1V maximum voltage enables EDs can be placed in series. However, placing EDs into series/parallel connection can give higher efficiency as shown in the efficiency curves. One of the ways to ensure the brightness uniformity is to pre-screen the EDs. PCB ayout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure the high pulse current in the power ground does not interference with the sensitive signals connected to Signal Ground. Both grounds should only be connected at one point right at the chip. The heavy current paths ( -- X pin- PGND, and --D-C 2 -PGND) should be as short as possible. The trace connected to the pin is most important. The current sense resister R 1 should be very close to the pin When the trace is long, use a small filter capacitor close to the pin. The heat of the IC is mainly dissipated through the PGND pin. Maximizing the copper area around the plane is preferable. In addition, a solid ground plane is always helpful for the EMI performance. FN2 Rev 0.00 Page 10 of 12

11 TSOT Package Outline Drawing FN2 Rev 0.00 Page 11 of 12

12 MSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at < Copyright Intersil Americas C 200. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN2 Rev 0.00 Page 12 of 12