Features. BAAA -40 to Ld TSOT Tape and Reel (Pb-Free) BAAA -40 to Ld TSOT Tape and Reel (Pb-Free)

Transcription

1 E51 White ED Step-Up Regulator NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPACEMENT PART IS96 DATASHEET FN112 Rev 5.00 The E51 is a constant current boost regulator specially designed for driving white EDs. It can drive EDs in series or up to 12 EDs in parallel/series configuration and achieves efficiency up to 91%. The brightness of the EDs is adjusted through a voltage level on the CNT pin. When the level falls below 0.1V, the chip goes into shut-down mode and consumes less than 1µA of supply current for less than 5.5V. The E51 is available in the d TSOT and d MSOP packages. The TSOT package is just 1mm high, compared to 1.5mm for the standard SOT2 package. Features 2.6V to 1.2V input voltage 1V maximum output voltage Drives up to 12 EDs 1MHz switching frequency Up to 91% efficiency 1µA maximum shut-down current Dimming control d TSOT and d MSOP packages Pb-free available (RoHS compliant) Applications PDAs Cellular phones Digital cameras White ED backlighting Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # E51IWT-T* 9-0 to +5 d TSOT Tape and Reel MDP009 E51IWT-TA* 9-0 to +5 d TSOT Tape and Reel MDP009 E51IWTZ-T* (See Note) E51IWTZ-TA* (See Note) BAAA -0 to +5 d TSOT Tape and Reel (Pb-Free) BAAA -0 to +5 d TSOT Tape and Reel (Pb-Free) MDP009 MDP009 E51IY d -0 to +5 d MSOP MDP00 E51IY-T* d -0 to +5 d MSOP Tape and Reel MDP00 E51IY-T1* d -0 to +5 d MSOP Tape and Reel MDP00 E51IYZ (See Note) E51IYZ-T* (See Note) E51IYZ-T1* (See Note) BAABA -0 to +5 d MSOP (Pb-Free) BAABA -0 to +5 d MSOP Tape and Reel (Pb-Free) BAABA -0 to +5 d MSOP Tape and Reel (Pb-Free) MDP00 MDP00 MDP00 *Please refer to TB for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MS classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN112 Rev 5.00 Page 1 of 12

2 E51 Pinouts Typical Connection COMP 1 E51 ( D TSOT) TOP VIEW VIN 2.6V TO 5.5V C 1.µF µh D C 2 CNT 2 6 SGND VIN X X 5 PGND 1 E51 ( D MSOP) TOP VIEW CNT V CTR C CNT COMP PGND SGND R 1 5 VIN 2 COMP PGND 6 X SGND 5 FN112 Rev 5.00 Page 2 of 12

3 E51 Absolute Maximum Ratings (T A = +25 C) COMP, CNT, to SGND V to +6V to SGND V V OUT to SGND V X to PGND V SGND to PGND V to +0.V Storage Temperature C to +150 C Ambient Operating Temperature C to +5 C Pb-Free Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications = V, V O = 12V, C 1 =.µf, = µh, C 2 =, C =, R 1 = 5, T A =+ 25 C, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Input Voltage V I Q1 Total Input Current at Shut-down V CNT = 0V 1 µa I Q1 Quiescent Supply Current at V O Pin V CNT = 1V, load disconnected ma I COMP COMP Pin Pull-up Current COMP connected to SGND µa V COMP COMP Voltage Swing V I CNT CNT Shut-down Current CNT = 0V 1 µa V CNT1 Chip Enable Voltage 20 mv V CNT2 Chip Disable Voltage 100 mv I OUT_ACCURACY V CNT = 1V V CNT = 1V ma V OUT1 Over-voltage Threshold V OUT rising V V OUT2 Over-voltage Threshold V OUT falling, with resistive load V IX MOSFET Current imit 500 ma R DS_ON MOSFET On-resistance 0. I EAK MOSFET eakage Current V CNT = 0V, V X = 12V 1 µa F S Switching Frequency khz D MAX Maximum Duty Ratio V CNT = 2V, I S = 0 5 % I Input Bias Current 1 µa I O / ine Regulation = 2.6V - 5.5V 0.0 %/V Pin Descriptions D TSOT D MSOP PIN NAME DESCRIPTION 1 COMP Compensation pin. A compensation cap (00pF to ) is normally connected between this pin and SGND. 2 CNT Control pin for dimming and shut-down. A voltage between 250mV and 5.5V controls the brightness, and less than 100mV shuts down the converter. 5 Output voltage sense. Use for over voltage protection. 6 X Inductor connection pin. The drain of internal MOSFET. 5 PGND Power Ground pin. The source of internal MOSFET. 6 SGND Signal Ground. Ground pin for internal control circuitry. Needs to connect to PGND at only one point. 1 Current sense pin. Connect to sensing resistor to set the ED bias current. 2 VIN Power supply for internal control circuitry. FN112 Rev 5.00 Page of 12

4 E51 Block Diagram 2.6V TO 5.5V C IN.µF REFERENCE GENERATOR 1MHz OSCIATOR THERMA SHUTDOWN OVER-VOTAGE PROTECTION V OUT µh X C COMP COMP + BOOST I-SENSE PWM OGIC I(ED) C OUT PWM SIGNA V CNT CNT 61k START-UP CONTRO ERROR AMP + - PGND C S 5 50k SGND Typical Performance Curves All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a V CNT = 0V, 0.1V WHITE EDs DISCONNECTED F S (MHz) I IN (µa) (V) (V) FIGURE 1. SWITCHING FREQUENCY vs FIGURE 2. QUIESCENT CURRENT FN112 Rev 5.00 Page of 12

5 E51 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a I ED (ma) V CNT (V) I ED (ma) V CNT = 1V (V) FIGURE. I ED vs V CNT FIGURE. I ED vs BAT5HT1.µF µh 2 EDs IN A SERIES =.2V V CTR VIN X CNT PGND = 2.V =COICRAFT PO10-CM FIGURE 5A. 2 EDs IN A SERIES FIGURE 5. FIGURE 5B. EFFICIENCY vs I O.µF µh BAT5HT1 EDs IN A SERIES V CTR VIN X CNT PGND =.2V = 2.V = COICRAFT PO10-CM FIGURE 6A. EDs IN A SERIES FIGURE 6. FIGURE 6B. EFFICIENCY vs I O FN112 Rev 5.00 Page 5 of 12

6 E51 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a BAT5HT1.µF µh EDs IN A SERIES =.2V V CTR VIN X CNT PGND =.V = 2.V = COICRAFT PO10-CM ED CURRENT (ma) FIGURE A. EDs IN A SERIES FIGURE. FIGURE B. EFFICIENCY vs I O BAT5HT1.µF µh 2 EGS OF 2 EDs IN A SERIES =.2V VIN X 5 5 V CTR CNT PGND = 2.V = COICRAFT PO10-CM FIGURE A. 2 EGS OF 2 EDs IN A SERIES FIGURE. FIGURE B. EFFICIENCY vs I O BAT5HT1.µF µh 2 EGS OF EDs IN A SERIES =.2V VIN X 5 5 V CTR CNT PGND = 2.V = SUMIDA CMD1D1-µH FIGURE 9A. 2 EGS OF EDs IN A SERIES FIGURE 9. FIGURE 9B. EFFICIENCY vs I O FN112 Rev 5.00 Page 6 of 12

7 E51 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a.µf µh BAT5HT1 2 EGS OF EDs IN A SERIES VIN X 5 5 V CTR CNT PGND =.2V 5 0 = 2.V 5 =SUMIDA CMD1D1-µH FIGURE 10A. 2 EGS OF EDs IN A SERIES FIGURE 10. FIGURE 10B. EFFICIENCY vs I O BAT5HT1.µF 15µH EGS OF 2 EDs IN A SERIES 95 VIN X V CTR CNT PGND =.2V = 2.V = SUMIDA CMD1D1-15µH FIGURE 11A. EGS OF 2 EDs IN A SERIES FIGURE 11. FIGURE 11B. EFFICIENCY vs I O BAT5HT1.µF 15µH EGS OF EDs IN A SERIES 95 VIN X =.2V V CTR CNT PGND =2.V =SUMIDA CMD1D1-15µH FIGURE 12A. EGS OF EDs IN A SERIES FIGURE 12. FIGURE 12B. EFFICIENCY vs I O FN112 Rev 5.00 Page of 12

8 E51 Typical Performance Curves (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a BAT5HT1.µF 15µH EGS OF EDs IN A SERIES 95 VIN X =.2V V CTR CNT PGND =2.V =SUMIDA CMD1D1-15µH FIGURE 1A. EGS of EDs in a SERIES FIGURE 1. FIGURE 1B. EFFICIENCY vs I O Waveforms All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a C = 00pF I IN 50mA/DIV 2V/DIV I IN 50mA/DIV V CNT 1V/DIV V CNT 1V/DIV I ED 10mA/DIV I ED 10mA/DIV 10ms/DIV FIGURE 1. START-UP 0.1ms/DIV FIGURE 15. SHUT-DOWN I ED = 15mA V CNT 2V 1V 10mV/DIV V O 1.2V 12.9V I 100mA/DIV 0mA V X 10V/DIV I ED 15mA V O 50mV/DIV 20ms/DIV FIGURE 16. TRANSIENT RESPONSE 1µs/DIV FIGURE 1. CONTINUOUS CONDUCTION MODE FN112 Rev 5.00 Page of 12

9 E51 Waveforms (Continued) All performance curves and waveforms are taken with C 1 =.µf, C 2 =, C =, = µf, =.V, V CNT = 1V, R 1 =5, EDs in a V CTR = 0.V, I ED = 5mA 10mV/DIV V O (5V/DIV) I 100mA/DIV V X 10V/DIV V COMP (1V/DIV) V O 50mV/DIV 1µs/DIV FIGURE 1. DISCONTINUOUS CONDUCTION MODE Detailed Description The E51 is a constant current boost regulator specially designed for driving white EDs. It can drive up to EDs in series or 12 EDs in parallel/series configuration and achieves efficiency up to 91%. The brightness of the EDs is adjusted through a voltage level on the CNT pin. When the level falls below 0.1V, the chip goes into shut-down mode and consumes less than 1µA of current for less than 5.5V. Steady-State Operation E51 is operated in constant frequency PWM. The switching is around 1MHz. Depending on the input voltage, the inductance, the type of EDs driven, and the ED s current, the converter operates at either continuous conduction mode or discontinuous conduction mode (see waveforms). Both are normal. Brightness Control ED s current is controlled by the voltage level on CNT pin (V CNT ). This voltage can be either a DC or a PWM signal with frequency less than 200Hz (for C = 00pF). When a higher frequency PWM is used, an RC filter is recommended before the CNT pin (see Figure 20). PWM SIGNA 100k CNT COMP FIGURE 20. PWM BRIGHTNESS CONTRO FIGURE 19. OVER VOTAGE PROTECTION (ED DISCONNECTED) The relationship between the ED current and CNT voltage level is as follows: V CNT I ED = R (EQ. 1) 1 When R 1 is 5, 1V of V CNT conveniently sets I ED to 15mA. The range of V CNT is 250mV to 5.5V. Shut-Down When V CNT is less than 100mV, the converter is in shutdown mode. The max current consumed by the chip is less than 1µA for less than 5.5V. Over-Voltage Protection When an ED string is disconnected from the output, V O will continue to rise because of no current feedback. When V O reaches 1V (nominal), the chip will shut down. The output voltage will drop. When V O drops below 16V (nominal), the chip will boost output voltage again until it reaches 1V. This hiccough continues until ED is applied or converter is shut down. When designing the converter, caution should be taken to ensure the highest operating ED voltage does not exceed 1V, the minimum shut-down voltage. There is no external component required for this function. Component Selection The input and output capacitors are not very important for the converter to operate normally. The input capacitance is normally 0.22µF -.µf and output capacitance 0.22µF -. Higher capacitance is allowed to reduce the voltage/current ripple, but at added cost. Use X5R or XR type (for its good temperature characteristics) of ceramic capacitors with correct voltage rating and maximum height. FN112 Rev 5.00 Page 9 of 12

10 E51 When choosing an inductor, make sure the inductor can handle the average and peak currents giving by following formulas (0% efficiency assumed): I O V O I AVG = where: I is the peak-to-peak inductor current ripple in Ampere inductance in µh FS switching frequency, typical 1MHz (EQ. 2) 1 I PK = I AVG + -- I 2 (EQ. ) V O I = V O F (EQ. ) S A wide range of inductance (6.µH - 6µH) can be used for the converter to function correctly. For the same series of inductors, the lower inductance has lower DC resistance (DCR), which has less conducting loss. But the ripple current is bigger, which generates more RMS current loss. Figure 11 shows the efficiency of the demo board under different inductance for a specific series of inductor. For optimal efficiency in an application, it is a good exercise to check several adjacent inductance values of your preferred series of inductors. For the same inductance, higher overall efficiency can be obtained by using lower DCR inductor. EFFICIENCY vs I O 5 =.V FOR DIFFERENT 1 = µh = 22µH = 15µH = 10µH 9 = Coilcraft PO10 SERIES 1mm HEIGHT FIGURE 21. EFFICIENCY OF DIFFERENT INDUCTANCE ( EDs IN A SERIES) The diode should be Schottky type with minimum reverse voltage of 20V. The diode's peak current is the same as inductor's peak current, the average current is I O, and RMS current is: I DRMS = I AVG I O Ensure the diode's ratings exceed these current requirements. (EQ. 5) White ED Connections One leg of EDs connected in series will ensure the uniformity of the brightness. 1V maximum voltage enables EDs can be placed in series. However, placing EDs into series/parallel connection can give higher efficiency as shown in the efficiency curves. One of the ways to ensure the brightness uniformity is to prescreen the EDs. PCB ayout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure the high pulse current in the power ground does not interference with the sensitive signals connected to Signal Ground. Both grounds should only be connected at one point right at the chip. The heavy current paths ( -- X pin-pgnd, and --D-C 2 -PGND) should be as short as possible. The trace connected to the pin is most important. The current sense resister R 1 should be very close to the pin When the trace is long, use a small filter capacitor close to the pin. The heat of the IC is mainly dissipated through the PGND pin. Maximizing the copper area around the plane is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on the principle. Please refer to the E51 Application Brief for the layout. FN112 Rev 5.00 Page 10 of 12

11 E51 TSOT Package Family C D 2X C 5 E1 SEATING PANE 0.10 C NX e N C A-B 2X (1) A 6 2 e1 (N/2) E D 0.25 C 2X N/2 TIPS B ddd M C A-B D b NX D 1 H A1 A2 MDP009 TSOT PACKAGE FAMIY MIIMETERS SYMBO TSOT5 TSOT6 TSOT TOERANCE A Max A ±0.05 A ±0.0 b ±0.0 c /-0.00 D Basic E Basic E Basic e Basic e Basic ± Reference ddd N 5 6 Reference Rev. B 2/0 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included.. This dimension is measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y1.5M Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT only). 6. TSOT5 version has no center lead (shown as a dashed line). A GAUGE PANE 0.25 c ± FN112 Rev 5.00 Page 11 of 12

12 E51 Mini SO Package Family (MSOP) 0.25 M C A B A D (N/2)+1 N MDP00 MINI SO PACKAGE FAMIY MIIMETERS SYMBO MSOP MSOP10 TOERANCE NOTES A Max. - A ± E E1 PIN #1 I.D. A ± b / c ± B 1 (N/2) D ±0.10 1, E.. ± E ±0.10 2, C e H e Basic ± SEATING PANE 0.10 C N EADS c 1 b SEE DETAI "X" 0.0 M C A B A Basic - N 10 Reference - Rev. D 2/0 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included.. Dimensions D and E1 are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y1.5M-199. A2 GAUGE PANE 0.25 A1 DETAI X ± Copyright Intersil Americas C All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO01 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN112 Rev 5.00 Page 12 of 12