NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package
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1 NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package Description: The NTE74S188 Schottky PROM memory is organized in the popular 32 words by 8 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs present the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. Features: Advanced Titanium Tungsten (Ti W) Fuses Schottky Clamped for High Speed Address access 35ns Typ Enable access 25ns Typ PNP Inputs Reduce Input Loading All DC and AC Parameters Guaranteed over Temperature Absolute Maximum Ratings: (Note 1) Supply Voltage (Note 2), V CC V to +7V Input Voltage (Note 2), V IN V to +5.5V Voltage (Note 2), V O V to +5.5V Storage Temperature, T stg to +150 C Lead Temperature (During Soldering, 10sec), T L C Recommended Operating Conditions: Supply Voltage, V CC Minimum V Maximum V Ambient Temperature, T A... 0 to +70 C Logical 0 Input Voltage (Low) Minimum... 0V Maximum V Logical 1 Input Voltage (High) Minimum V Maximum V Note 1. Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at these values. Note 2. These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
2 DC Electrical Characteristics: (Note 3) Parameter Symbol Test Conditions Min Typ Max Unit Input Load Current, All Inputs I IL V CC = Max, V IN = 0.45V A Input Leakage Current, All Inputs I IH V CC = Max, V IN = 2.7V 25 A Input Leakage Current, All Inputs I I V CC = Max, V IN = 5.5V 1.0 ma Low Level Voltage V OL V CC = Min, I OL = 16mA V Low Level Input Voltage V IL 0.80 V High Level Input Voltage V IH 2.0 V Leakage Current (Note 5) I CEX V CC = Max, V CEX = 2.4V 50 A V CC = Max, V CEX = 5.5V 100 A Input Clamp Voltage V C V CC = Min, I IN = 18mA V Input Capacitance C IN V CC = 5V, V IN = 2V, T A = 25 C, 4.0 pf 1MHz Capacitance C O V CC = 5V, V O = 2V, T A = 25 C, 6.0 pf 1MHz, OFF Power Supply Current I CC V CC = Max, All Inputs Grounded, All s Open ma AC Electrical Characteristics: (With Standard Load, V CC = 5V 10%, T A = 0 to +70 C) Parameter Symbol Test Conditions Min Typ Max Unit Address Acess Time t AA ns Enable Access Time t EA ns Enable Recovery Time t ER ns Note 3. These limits apply over the entire operating range unless otherwise specified. All typical values are for V CC = 5V and T A = +25 C. Note 4. During I SC measurement, only one output at a time should be grounded. Permanent damage may otherwise result. Note 5. To measure V OH, I CEX, or I SC on an unprogrammed part, apply 10.5V to either A0 (Pin10) or A4 (Pin14). Block Diagram A4 A3 A2 A1 A0 1/32 Decoder 256 Bit Array 32 x 8 Bit Memory Matrix E1 Enable Gate O8 O7 O6 O5 O4 O3 O2 O1
3 Step by Step NTE74S188 Schottky PROM Programming Procedure: 1. Apply steady state supply voltage (V CC = 5V) and address the word to be programmed. 2. Verify that the bit location needs to be programmed. If not, proceed to the next bit. 3. If the bit requires programming, disable the outputs by applying a high logic level voltage to the chip select input(s). 4. Only one bit location is programmed at a time. Connect each output not being programmed to 5V through 3.9k and apply the voltage specified in the table to the output to be programmed. Maximum current into the programmer output is 150mA. 5. Step V CC to 9.25 nominal. Maximum supply current required during programming is 750mA. 6. Apply a low logic level voltage to the chip select input(s). This should occur between 1 s and 1ms after V CC has reached its 9.25 level. See programming sequence of Figure After the X pulse time is reached, a high logic level is applied to the chip select input(s) to disable the outputs. 8. Within the range of 1 s to 1ms after the chip select input(s) reach a high logic level, V CC should be stepped down to 5V at which level verification can be accomplished. 9. The chip select input(s) may be taken to a low logic level (to permit program verification) 1 s or more after V CC reaches its steady state value of 5V. 10. At a Y pulse duty cycle of 35% or less, repeat steps 1 through 8 for each output where it is desired to program a bit. 11. Verify accurate programming of every word after all words have been programmed using V CC values of 4.5V and 5.5V. Note 6. Only one programming attempt per bit is recommended. Recommended Conditions for Programming: (Do not test or you may program the device.) Parameter Min Typ Max Unit Supply Voltage (Note 7), V CC Steady State V Program Pulse V Input Voltage High Level, V IH V Termination of All s Except the One to be Programmed Low Level, V IL V See Load Circuit (Figure 1) Voltage Applied to to be Programmed, V O(pr) V Duration of V CC Programming Pulse X (Note 8, See Figure 2) s Programming Duty Cycle for Y Pulse % Ambient Temperature C Note 7. Voltage values are with respect to network GND terminal. The supply voltage rating does not apply during programming. Note 8. Programming is guaranteed if the pulse applied as 98 s in duration.
4 Figure 1. Load Circuit 5V 3.9k OUTPUT Load circuit for each output not being programmed or for program verification. Figure 2. Voltage Waveforms for Programming Verify Need to Program V CC 1 s to 1ms S Y X 1 s to 1ms 3V Typical Verify Program Remove V CC to Reduce Average Power 9.25V 5V 0V V IH Apply V O(pr) Remove V O(pr) V IL
5 Pin Connection Diagram O V CC O E1 O A4 O A3 O A2 O A1 O A0 GND 8 9 O (22.0) Max.260 (6.6) Max.200 (5.08) Max.100 (2.54).099 (2.5) Min.700 (17.78)
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Pin Connection (Top View)
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I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7
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Obsolete Product(s) - Obsolete Product(s)
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Obsolete Product(s) - Obsolete Product(s)
SINGLE 2-INPUT NAND GATE 5V TOLERANT INPUTS HIGH SPEED: t PD = 4.7ns (MAX.) at V CC =3V LOW POWER DISSIPATION: I CC =1µA (MAX.)atT A =25 C POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT
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