! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements

Size: px
Start display at page:

Download "! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements"

Transcription

1 EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams! esign Rules! tandard Cells! CMO Process Enhancements 2 Big Idea! ystematic construction of any gate from transistors with CMO PUN and PN! Hierarchical design process in three domains (behavioural, structural, and physical) allows for complicated designs motivated cost as a function of performance, yield and design time tatic CMO Gate tructure! rives rail-to-rail " Power rails are V dd and Gnd " output is V dd or Gnd! Input connects to gates # load is capacitive! Once output node is charged doesn t use energy (no static current only leakage)! Output actively driven 3 4 Ideal nmo and pmo Characteristics MOFET N-Type, P-Type G B g = 0 g = 1 g = 1 g = 1! N negative carriers " electrons! witch turned on positive V G! P positive carriers " holes! witch turned on negative V G g G g B a b a g = 0 g = 0 b a g = 1 g = 0 5 V th,n > 0 V G > V th,n to conduct V th,p < 0 V G < V th,p to conduct 6 1

2 ymmetry ymmetry! NMO: " Electrons are carriers " Electrons flow from source-to-drain " From lowest voltage#highest " rain is most positive terminal " Current flows from drain-tosource! PMO: " Holes are carriers " positively " Holes flow from source#drain " Flow from highest voltage#lowest " rain is most negative terminal " Current flows from source-todrain! ymmetric evice " Like a resistor, doesn t know difference between two ends " rain and source are defined by circuit connections! ymmetric evice " Like a resistor, doesn t know difference between two ends " rain and source are defined by circuit connections 7 8 MO Transistors Typical N-Well CMO Process G B G B 9 10 Typical N-Well CMO Process Interconnect Cross ection 11 ITR

3 CMO Layers NMO vs PMO! tandard n-well Process " Active (iffusion) (rain/ource regions)! NMO built on p substrate! PMO built on n substrate " Polysilicon (Gate Terminals) " Needs an N-well " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMO bulk region) " n elect (used with active to create n-type diffusion) " p elect (used with active to create p-type diffusion) MO Layout Well, Active, elect MO Layout Well, Active, elect w/ Poly Typical N-Well CMO Process CMO Layers! tandard n-well/p-substrate Process " Active (iffusion) (rain/ource regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMO bulk region) " n elect (used with active to create n-type diffusion) " p elect (used with active to create p-type diffusion)

4 Wiring and Contact Layout ubstrate and Well Contacts! Properties " et Well and ubstrate Voltages to Vdd and Gnd " Prevent Forward Biasing and Latch-Up G " Must Be at Least One per Well " hould Be Placed Regularly B iffusion (Active) Contact Poly Contact Via (metal1-metal2) Layout Example: CMO Inverter Layout Example: CMO Inverter! et Pitch (place well and power/ground busses)! Add Transistors (active, select and poly) Layout Example: CMO Inverter Layout Example: CMO Inverter! Make Connections (poly, metal, and contacts)! Add ubstrate and Well Contacts

5 Layout Example: CMO Inverter Example: Mystery Gate! Add External Wiring and Resize Example: NAN Gate Example: NAN Gate (Horizontal) Layout Example ymbolic Layout! How many transistors?! tick diagrams capture spatial relationships, but abstract away design rules (coming up next )! What are the relative sizes?! How are they connected?! What function does this gate perform? " How many NMO? PMO? / connections?

6 Layout esign Rules esign Rules! Physical Layer " esign Rules are a set of process-specific geometric rules for preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries intended by the chip designers! Purpose " Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and maximize yield! esign Rule Waiver " Explicit permission granted by the fabrication organization to the design organization to violate certain design rules or to allow certain design rule errors on a given design! Minimum eparation [A] " Intralayer (all layers) " Interlayer (active to poly/well/select) " From Transistor! Minimum Width (all layers) [B]! Minimum Overlap [C] " Past Transistor (poly, active) " Around Contact Cut (all contacted layers) " Around Active (well, select)! Exact ize (contact cuts) [] calable CMO Rules Width/pacing esign Rules! efinition " esign Rules Based on a Unitless Parameter (λ) " λ cales with Process Feature ize N-Well Rules Active Rules Poly Rules " λ = 0.5*L min " Example: λ = 0.6um in a 1.2um Process! Advantages " implifies esign - Requires Learning Only One et of esign Rules " Facilitates Translating esigns between Processes Metal Rules Contact esign Rules Potential Consequences of esign Rule Violations! Inter-Layer esign Rule Origins Intended Transistor Catastrophic Error Unintended misalignment cause ource-rain short circuit Intended Unrelated Poly & iffusion Catastrophic Error Unintended overlap cause fabrication of a parasitic Transistor

7 Potential Consequences of esign Rule Violations esign Capture Tools! Inter-Layer esign Rule Origins Both Metal 1 & iffusion Intended Contact Alignment Contact and Via Masks M1 contact to n-diffusion M1 contact to p-diffusion M1 contact to poly Mn contact to Mn-1 for n = 2, 3,.. -> Contact Mask -> Via Mask Both Metal 1 & iffusion Mask misalignment Error Unintended misalignment cause poor contact! Hardware escription Languages (HL) & " capture a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description (eg. VHL, Verilog)! chematic capture " capture a structural, hierarchical graphical representation of the design netlist (eg. Cadence Composer)! Layout " capture a hierarchical view of the physical geometric aspect of a design. The units of hierarchy are called cells, and have physical extent (size). In general, good design requires that only one cell contain the design info for a particular area of the chip (eg. Cadence Virtuoso) Testing/Verification Rules Checking! Formal verification is used to show that the design satisfies a formal description of what it should do! imulation is used to show that the design is functional on some well selected set of input vectors! Timing analysis is used to predict design performance! Complex designs invariably suffer design and design entry errors. There are a number of tools and methodologies to detect and correct " Physical esign Rules Checking (RC) checks for design rule violations such as minimum spacing etc. RC checking is complicated by hierarchy and overlap between cells " Electrical Rule Checking (ERC) checks for violations such as shorts between Vdd and GN, opens, and so on " Layout vs. chematic (LV) checks for a one-to-one correspondence between transistor schematic and the layout RC Error Example Circuit Extraction! Circuit extraction extracts a schematic representation of a layout, including transistors, wires, and possibly wire and device resistance and capacitance.! Circuit extraction is used for LV, and for spice simulation of layouts

8 Circuit Extraction Circuit Extraction 43 Example: NAN Gate (Horizontal) 44 tandard Cells! Lay out gates so that heights match " "! Motivation: automated place and route " 45 tandard Cell Area Rows of adjacent cells tandardized sizes EA tools convert HL to layout 46 tandard Cell Layout Example All cells uniform height inv nand3 Cell area Width of channel determined by routing

9 CMO Process Enhancements Interconnect Cross ection! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias 49 ITR Local Interconnect CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs ITR CMO Poly-Poly Capacitors Resistors W L

10 CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! evices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET High-K dielectric io 2 ielectric Poly gate MOFET ielectric constant=3.9 High-K ielectric Metal gate MOFET ielectric constant= High-K dielectric urvey 22nm 3 FinFET Transistor Wong/IBM J. of R&, V46N2/3P , High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance 58 CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! evices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET! ilicon on insulator process (OI) " Fabricate on insulator for high speed/low leakage Big Idea! Layouts are physical realization of circuit " Geometry tradeoff " Can decrease spacing at the cost of yield " esign rules! Can go from circuit to layout or layout to circuit by inspection! Can draw stick diagram for any logic gate to help plan layout

11 Admin! HW 1 due tonight! HW 2 due next week 1/25 " Posted tonight after class 61 11

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture

More information

Sticks Diagram & Layout. Part II

Sticks Diagram & Layout. Part II Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners.

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners. ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and Area Today Coping with Variation (from last time) Layout Transistors Gates Design rules Standard

More information

EE 330 Lecture 5. Improved Device Models Propagation Delay in Logic Circuits

EE 330 Lecture 5. Improved Device Models Propagation Delay in Logic Circuits EE 330 Lecture 5 Improved evice Models Propagation elay in Logic Circuits Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation rain rain ulk Cross-ectional View n-channel MOFET

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers

More information

MOSFETS: Gain & non-linearity

MOSFETS: Gain & non-linearity MOFET: ain & non-linearity source gate Polysilicon wire Heavily doped (n-type or p-type) diffusions W Inter-layer io 2 insulation Very thin (

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

LECTURE 14. (Guest Lecturer: Prof. Tsu-Jae King) Last Lecture: Today:

LECTURE 14. (Guest Lecturer: Prof. Tsu-Jae King) Last Lecture: Today: LECTURE 14 (uest Lecturer: Prof. Tsu-Jae King) Last Lecture: emiconductors, oping PN Junction iodes iode tructure and I vs. V characteristics iode Circuits Today: N-Channel MOFET tructure The MOFET as

More information

CS/ECE 5710/6710. Composite Layout

CS/ECE 5710/6710. Composite Layout CS/ECE 5710/6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different

More information

EE 330 Lecture 7. Design Rules

EE 330 Lecture 7. Design Rules EE 330 Lecture 7 Design Rules Last time: Response time of logic gates A Y C L t R C HL SWn L t R C LH SWp L C L proportional to #gates driven to avg input cap of gates R SW proportional length/width Last

More information

VLSI Design. Static CMOS Logic

VLSI Design. Static CMOS Logic VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM Review: MOS Process at a Glance efine active areas Etch and fill trenches

More information

Lecture 9: Cell Design Issues

Lecture 9: Cell Design Issues Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the

More information

Layout - Line of Diffusion. Where are we? Line of Diffusion in General. Line of Diffusion in General. Stick Diagrams. Line of Diffusion in General

Layout - Line of Diffusion. Where are we? Line of Diffusion in General. Line of Diffusion in General. Stick Diagrams. Line of Diffusion in General Where are we? Lots of Layout issues Line of diffusion style Power pitch it-slice pitch Routing strategies Transistor sizing Wire sizing Layout - Line of Diffusion Very common layout method Start with a

More information

Chapter 1. Introduction

Chapter 1. Introduction EECS3611 Analog Integrated Circuit esign Chapter 1 Introduction EECS3611 Analog Integrated Circuit esign Instructor: Prof. Ebrahim Ghafar-Zadeh, Prof. Peter Lian email: egz@cse.yorku.ca peterlian@cse.yorku.ca

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

EE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30

EE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30 EE 330 Lecture 44 igital Circuits Ring Oscillators Sequential Logic Array Logic Memory Arrays Final: Tuesday May 2 7:30-9:30 Review from Last Time ynamic Logic Basic ynamic Logic Gate V F A n PN Any of

More information

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT 2-8.1 2-8.2 Spiral 2 8 Cell Mark Redekopp earning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware HPTER II-6 MO MO WITHE WITH NETWORK -WITHE IN ERIE -WITHE IN PRLLEL -INPUT ELETOR 883: dvanced Digital Design for Embedded Hardware Lecture : MO Transistors and Layout The idea is to use the series and

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

Topic 2. Basic MOS theory & SPICE simulation

Topic 2. Basic MOS theory & SPICE simulation Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/

More information

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

Design Rules, Technology File, DRC / LVS

Design Rules, Technology File, DRC / LVS Design Rules, Technology File, DRC / LVS Prof. Dr. Peter Fischer VLSI Design: Design Rules P. Fischer, TI, Uni Mannheim, Seite 1 DESIGN RULES Rules in one Layer Caused by manufacturing limits (lithography,

More information

Wiring Parasitics. Contact Resistance Measurement and Rules

Wiring Parasitics. Contact Resistance Measurement and Rules Wiring Parasitics Contact Resistance Measurement and Rules Connections between metal layers and nonmetal layers are called contacts. Connections between metal layers are called vias. For non-critical design,

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture

More information

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Projects. Groups of 3 Proposals in two weeks (2/20) Topics: Lecture 5: Transistor Models

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Projects. Groups of 3 Proposals in two weeks (2/20) Topics: Lecture 5: Transistor Models EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 5: Transistor Models Projects Groups of 3 Proposals in two weeks (2/20) Topics: Soft errors in datapaths Soft errors in memory Integration

More information

Review: CMOS Logic Gates

Review: CMOS Logic Gates Review: CMOS Logic Gates INV Schematic NOR Schematic NAND Schematic + Vsg - pmos x x Vin Vout = Vin y + Vgs - nmos CMOS inverts functions CMOS Combinational Logic x g(x,y) = x + y use DeMorgan relations

More information

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System 1 Raj Kumar Mistri, 2 Rahul Ranjan, 1,2 Assistant Professor, RTC Institute of Technology, Anandi, Ranchi, Jharkhand,

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit

More information

Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits

Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:

More information

EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic EE 330 Lecture 5 Other Logic Styles complex logic gates pass transistor logic Improved evice Models Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation Source Gate rain rain

More information

CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC

CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC 94 CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC 6.1 INTRODUCTION The semiconductor digital circuits began with the Resistor Diode Logic (RDL) which was smaller in size, faster

More information

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector

Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector Sanjay Kumar Wadhwa 1, G.K. Siddhartha 2, Anand Gaurav 3 Freescale Semiconductor India Pvt. Ltd. 1 sanjay.wadhwa@freescale.com,

More information

I/O Design EE141. Announcements. EE141-Fall 2006 Digital Integrated Circuits. Class Material. Pads + ESD Protection.

I/O Design EE141. Announcements. EE141-Fall 2006 Digital Integrated Circuits. Class Material. Pads + ESD Protection. EE141-Fall 2006 Digital Integrated Circuits nnouncements Homework 9 due on Thursday Lecture 26 I/O 1 2 Class Material Last lecture Timing Clock distribution Today s lecture I/O Power distribution Intro

More information

Fundamentals of Integrated Circuit Design

Fundamentals of Integrated Circuit Design 1. Definitions Integrated circuits Fundamentals of Integrated Circuit Design An integrated circuit (IC) is formed by components and interconnections that are fabricated on a single silicon piece of semiconductor,

More information

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts.

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts. UNIT III VLSI CIRCUIT DESIGN PROCESSES In this chapter we will be studying how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: N-diffusion P-diffusion

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

ECE380 Digital Logic. Logic values as voltage levels

ECE380 Digital Logic. Logic values as voltage levels ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams

EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams EE 330 Lecture 5 Other Logic Styles Improved evice Models Stick iagrams Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain rain Gate n-channel MOSFET

More information

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules

More information

Designing Information Devices and Systems II Fall 2017 Note 1

Designing Information Devices and Systems II Fall 2017 Note 1 EECS 16B Designing Information Devices and Systems II Fall 2017 Note 1 1 Digital Information Processing Electrical circuits manipulate voltages (V ) and currents (I) in order to: 1. Process information

More information

2. (2 pts) What is the major reason static CMOS NAND gates are often preferred over static CMOS NOR gates?

2. (2 pts) What is the major reason static CMOS NAND gates are often preferred over static CMOS NOR gates? EE 330 Final Exam Spring 05 Name Instructions: Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 0 questions and 8 problems. There are two points allocated to each question.

More information

EC 1354-Principles of VLSI Design

EC 1354-Principles of VLSI Design EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of

More information

Technology, Jabalpur, India 1 2

Technology, Jabalpur, India 1 2 1181 LAYOUT DESIGNING AND OPTIMIZATION TECHNIQUES USED FOR DIFFERENT FULL ADDER TOPOLOGIES ARPAN SINGH RAJPUT 1, RAJESH PARASHAR 2 1 M.Tech. Scholar, 2 Assistant professor, Department of Electronics and

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Penn ESE 570 Spring 2016 Khanna Lecture Outline! Design Methodologies " Hierarchy, Modularity,

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

Electronics Basic CMOS digital circuits

Electronics Basic CMOS digital circuits Electronics Basic CMOS digital circuits Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED October 21, 2014 1 / 30 Introduction The topics covered today: The inverter: the simplest

More information

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers 6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005

More information

3-2-1 Contact: An Experimental Approach to the Analysis of Contacts in 45 nm and Below. Rasit Onur Topaloglu, Ph.D.

3-2-1 Contact: An Experimental Approach to the Analysis of Contacts in 45 nm and Below. Rasit Onur Topaloglu, Ph.D. 3-2-1 Contact: An Experimental Approach to the Analysis of Contacts in 45 nm and Below Rasit Onur Topaloglu, Ph.D. Outline Introduction and Motivation Impact of Contact Resistance Test Structures for Contact

More information

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R R 6 W 1 C C 3 D R t 1 R R t 2 R R t

More information

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques: Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward

More information

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance

More information

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter

More information

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Introduction - So far, have considered transistor-based logic in the face of technology scaling - Interconnect effects are also of concern

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing

More information

BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows

BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows Unit 3 BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows 1.Specification (problem definition) 2.Schematic(gate level design) (equivalence check) 3.Layout (equivalence

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

CS/EE 181a 2010/11 Lecture 1

CS/EE 181a 2010/11 Lecture 1 CS/EE 181a 2010/11 Lecture 1 CS/EE 181 is about designing digital CMOS systems. Functional Specification Approximate domain of CS181 Circuit Specification Simulation Architectural Specification Abstract

More information

EE 434 Lecture 2. Basic Concepts

EE 434 Lecture 2. Basic Concepts EE 434 Lecture 2 Basic Concepts Review from Last Time Semiconductor Industry is One of the Largest Sectors in the World Economy and Growing All Initiatives Driven by Economic Opportunities and Limitations

More information

30 ma flash LDO voltage regulator (output voltage 1.8 ± 0.2 V)

30 ma flash LDO voltage regulator (output voltage 1.8 ± 0.2 V) SPECIFICATION 1 FEATURES Global Foundries CMOS 55 nm Low drop out Low current consumption Two modes operations: Normal, Economy Mode operation Bypass No discrete filtering capacitors required (cap-less

More information

ECEN474/704: (Analog) VLSI Circuit Design Fall 2016

ECEN474/704: (Analog) VLSI Circuit Design Fall 2016 ECEN474/704: (Analog) VLSI Circuit Design Fall 2016 Lecture 1: Introduction Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Turn in your 0.18um NDA form by Thursday Sep 1 No

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa atarina enter for Technology omputer Science & Electronics Engineering Integrated ircuits & Systems INE 5442 Lecture 16 MOS ombinational ircuits - 2 guntzel@inf.ufsc.br Pass

More information

Session 3: Solid State Devices. Silicon on Insulator

Session 3: Solid State Devices. Silicon on Insulator Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted

More information

UNIT-III POWER ESTIMATION AND ANALYSIS

UNIT-III POWER ESTIMATION AND ANALYSIS UNIT-III POWER ESTIMATION AND ANALYSIS In VLSI design implementation simulation software operating at various levels of design abstraction. In general simulation at a lower-level design abstraction offers

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Lecture 0: Introduction

Lecture 0: Introduction Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus

More information

Low On-Resistance Trench Lateral Power MOS Technology

Low On-Resistance Trench Lateral Power MOS Technology Low On-Resistance Trench Lateral Power MO Technology Akio ugi Mutsumi awada Naoto Fujishima 1. Introduction Market demands for smaller sized, lighter weight, lower power consuming and higher efficiency

More information

UNIT-III GATE LEVEL DESIGN

UNIT-III GATE LEVEL DESIGN UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms

More information

Low Power, Area Efficient FinFET Circuit Design

Low Power, Area Efficient FinFET Circuit Design Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Abstract FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate

More information

5. CMOS Gates: DC and Transient Behavior

5. CMOS Gates: DC and Transient Behavior 5. CMOS Gates: DC and Transient Behavior Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 18, 2017 ECE Department, University

More information

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law

More information

Laser attacks on integrated circuits: from CMOS to FD-SOI

Laser attacks on integrated circuits: from CMOS to FD-SOI DTIS 2014 9 th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Laser attacks on integrated circuits: from CMOS to FD-SOI J.-M. Dutertre 1, S. De Castro 1, A. Sarafianos

More information

CMOS synchronous Buck switching power supply Raheel Sadiq November 28, 2016

CMOS synchronous Buck switching power supply Raheel Sadiq November 28, 2016 CMOS synchronous Buck switching power supply Raheel Sadiq November 28, 2016 Part 1: This part of the project is to lay out a bandgap. We previously built our bandgap in HW #13 which supplied a constant

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

Power dissipation in CMOS

Power dissipation in CMOS DC Current in For V IN < V TN, N O is cut off and I DD = 0. For V TN < V IN < V DD /2, N O is saturated. For V DD /2 < V IN < V DD +V TP, P O is saturated. For V IN > V DD + V TP, P O is cut off and I

More information

Session 10: Solid State Physics MOSFET

Session 10: Solid State Physics MOSFET Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)

More information