ISSCC 2003 / SESSION 6 / LOW-POWER DIGITAL TECHNIQUES / PAPER 6.2
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1 ISSCC 2003 / SESSION 6 / OW-POWER DIGITA TECHNIQUES / PAPER A Shared-Well Dual-Supply-Voltage 64-bit AU Yasuhisa Shimazaki 1, Radu Zlatanovici 2, Borivoje Nikoli 2 1 Hitachi, Tokyo Japan, now with SuperH, Tokyo Japan 2 University of California, Berkeley CA Power and power densities have constantly been increasing, which brings them to become primary constraints in present and future integrated circuit designs. A common goal is to use the design techniques that achieves the highest operating frequency with lowest power. A reduction in the supply voltage of a circuit decreases power dissipation, but degrades speed performance. The supply voltage can be selectively lowered by using a dualsupply technique [1], whereby a second, lower voltage can be supplied to non-critical timing paths without compromising performance. Additionally, this second voltage is employed to selectively reduce the power of gates that drive large switched capacitances with small impact on overall speed. Figure 6.2.1a shows a conventional dual-supply layout where high supply (V DDH ) and low supply (V DD ) are applied to two neighboring cells. The cells have to be placed in separate rows because of required well separation, resulting in an impractical layout for the datapath design. Figure 6.2.1b shows the circuit schematic and layout examples of a shared N-well dual-supply technique that is better suited to the datapaths. The power supply is split into V DDH and V DD rails. The N-well is always tied to V DDH, while the cells are supplied from either V DDH or V DD by simple via placement. Both V DDH and V DD cells can be placed in the same row, making this an area-efficient technique with no area overhead in a datapath. The main disadvantages of this method are reduced drive current of the PMOS transistors and issues with power routing. However, both are addressed through careful design. In the shared N-well technique, the delay of V DD circuits is additionally increased due to negative back-biasing of the PMOS transistors. Figure shows the simulated fanout-of-4 inverter (FO4-INV) delay and subthreshold current of a PMOS transistor. As V DD decreases, the delay increases, resulting in an 18% speed degradation at 1.2V, compared to a conventional, nonback-biased V DD circuit. Since this increase in delay significantly affects the performance of conventional CMOS logic, domino logic is preferred for this dual-supply approach. An additional benefit is that the PMOS leakage is reduced by two orders of magnitude. The second potential problem is in the increase of power rail resistances because of their reduced width. Although the dual supply technique reduces total power, the length of the rows between power straps has to be limited to avoid an increased IR drop. Added space between the two supply rails affects cell layout density for small cell heights. However, in datapaths, the cell height is usually determined by architectural and performance requirements; therefore, the datapath circuit cells are made tall enough to avoid any loss in density. A block diagram of a 64b AU module implemented in domino logic employing the proposed dual-supply technique is shown in Fig The AU module, similar to [2,3], consists of an AU, an output buffer and an input operand selector. The AU can execute arithmetic (add/sub) and logic (and/or/xor) functions. The carry path is implemented in the V DDH domain, while the partial sum generation and the logical unit are supplied from V DD. Carry signals are computed using a sparse radix-4 tree whose structure is shown in Fig Every fourth carry is calculated in the tree. While the full radix-4 tree suffers from a large number of complex carry-merge gates, the sparse implementation significantly reduces the gate and wire count while increasing the complexity of the sum computation. This sparse tree is particularly suitable for a dual-supply implementation, where the complex sum precompute gates are placed in the V DD domain. In this implementation they are in the critical path when V DD is lowered to 1.2V. While the V DDH gates can freely drive V DD gates, returning to V DDH domain requires level conversion. Domino level converters, similar to [4], are used in the sum selectors and the 9:1 multiplexers. Detailed circuit schematics of the output buffer and the 9:1 multiplexer are shown in Fig Since the forwarding interconnect is long with a high fanout load, the output buffer has a large power consumption. owering the supply on the buffer to 1.2V results in 56% energy reduction with 22% delay increase. However, this delay penalty corresponds to only 8% cycle time increase for the complete AU module. The datapath is organized using cells with a pitch of 18 metal-1 tracks in a bit slice. Since the carry is computed only for every fourth bit, the sum precompute cells and buffers are placed in empty rows, resulting in a very dense layout. A micrograph of the test chip is shown in Fig The chip uses a 1.8V, general-purpose 0.18µm 1P 5M CMOS process, with local interconnect technology. The chip includes 6 AU modules, to simulate the loading conditions of a 6-issue integer execution unit, control circuitry, clock drivers and test circuitry. An additional capacitance is added to simulate the cache and register file load. The size of the AU module is 200 x 760µm, while the overall chip size is 2mm x 1.5mm. With V DDH = V DD = 1.8V, the chip operates at its nominal frequency of 1.16GHz, corresponding to 13 FO-4-INV delays. Figure 6.2.7a summarizes the effect of the dual-supply operation on circuit speed and energy consumption. Single-supply operation is plotted as a reference where the supply is scaled down to meet the target delay. When the target delay is increased by 2.8%, total energy saving is 25.3% using dual supplies. A delay increase of 8.3% results in an energy savings of 33.3%. In comparison to a single reduced supply operation, the energy savings are 20.2% and 20.9% respectively. eakage power is reduced by 42% at V DD = 1.2V. Figure 6.2.7b illustrates the effect of the negative back-biasing of PMOS transistors. Acknowledgements This work was supported by Hitachi td. and MARCO C2S2. The authors thank ST Microelectronics for test chip fabrication. References [1] K. Usami and M. Horowitz, Clustered Voltage Scaling for ow-power Design, ISPED, pp. 3-8, Apr [2] S. Mathew et al., Sub-500ps 64b AUs in 0.18_m SOI/Bulk CMOS: Design & Scaling Trends, ISSCC Dig. Tech. Papers, pp , [3] E. Fetzer and T. Orton, A Fully-Bypassed 6-Issue Integer Datapath and Register File on an Itanium Microprocessor, ISSCC Dig. Tech. Papers, pp , [4] N. Tzartzanis et al., A 34Word x 64b 10R/6W Write-Through Self- Timed Dual-Supply-Voltage Register File, ISSCC Dig. Tech. Papers, pp , 2002.
2 ISSCC 2003 / February 10, 2003 / Salon / 2:00 PM D5E.44/!6#43:!#= N $M # AT/ U"1O% "?3@/A#=B.=:!#=34 6;3-.>/D5E.44!"!$ #" #$ D#-<34!R.>/*FG5HD%/>.438 $1M $ "1M " 1M 9#=B.=:!#=34 6;3-.>/D/E.44 " 1" 1" D#-<34!R.>/IJF)/H#SS 6?C@/);3-.>/D5E.44 Figure 6.2.1: Dual-supply circuit schematic options and layout. 1" "1 "1$ "1G "10 "1O $1 P%Q Figure 6.2.2: FO4-INV delay and PMOS leakage current. 94#9K/+.=1 HD%$ 9KM \]/JYZ 3!= 9K" [2"JYZ M2"JYZ +7 +.=1 3!= [2"JYZ $2"JYZ C!= + 7 9K$T9KN 9KG /+.=1 6,<?-3>!W5G/673-6.@ 6,</6.41 HD%" 73-:!34/6,< 6X6" 1M7* C!:0N 0$ " 9!= ]XI ]GXIG ]"0XI"0 ]0G 4#=+/E!-. 2/ 2/ 4#+!934/,=!:?3=>X#-XW#-@ S,=9:!#=?3>>/X/4#+!934/,=!:@ 6,<C 90N 60N 6" 6 )YJ)`( Figure 6.2.3: Block diagram of a 64-bit AU. Figure 6.2.4: Sparse radix-4 carry tree. 6,< 6,<C?;.3B8/4#3>@ 79!""#"$ 3!= HD%" HD%$ >#<!=#/4.B.4/9#=B.-:.-/?[2"/JYZ@ D#-<34!R.>/>.438 "1G "1N "1$ "1" "1 1[ $M # AT/ U"1O% "1$ "1 1O 10 1G 1$ D#-<34!R.>/.=.-+8 1O "1 "1$ "1G "10 "1O $1 P%Q Figure 6.2.5: Output buffer and domino level converter. Figure 6.2.6: Chip micrograph.
3 `=.-+8/P7bQ " [ O V 0 M G N > c##</:.<71 ),7748/B#4:3+./!6/B3-!.> U U$1 U"1O U"10 (.3K3+./I#E.-/PµdQ 0 M G N $ " 5G$e U"1O%T/c##</:.<71 >#<3!= >#<3!= $ 10 1O "1 "1$ "1G "10 \ AaA(` P=6Q?3@/\-3>.5#SS/C.:E..=/>.438/3=>/.=.-+81 "1 "1$ "1G "10 "1O $1 P%Q?C@/(.3K3+./-.>,9:!#=1 6 Figure 6.2.7: Measured results.
4 6;3-.>/D5E.44!" #"!$ Figure 6.2.1: Dual-supply circuit schematic options and layout.
5 N $M # AT/ U"1O% " $1M 6;3-.>/D/E.44 D#-<34!R.>/*FG5HD%/>.438 $ "1M " 1M 9#=B.=:!#=34 " 1" 1" D#-<34!R.>/IJF)/H#SS "1 "1$ "1G "10 "1O $1 P%Q 1" Figure 6.2.2: FO4-INV delay and PMOS leakage current.
6 94#9K/+.=1 HD%$ 9KM [2"JYZ 3!= \]/JYZ 3!= M2"JYZ 9K" +7 +.= K$T9KN 93--8/+.=1?-3>!W5G/673-6.@ 9KG ,< 6,</6.41 HD%" [2"JYZ $2"JYZ C!= 73-:!34/6,< 6X6" 1M7* 4#=+/E!-. 2/ 2/ 4#+!934/,=!:?3=>X#-XW#-@ S,=9:!#=?3>>/X/4#+!934/,=!:@ 6,<C Figure 6.2.3: Block diagram of a 64-bit AU.
7 C!:0N 0$ " 9!= ]XI ]GXIG ]"0XI"0 ]0G 90N 60N 6" 6 )YJ)`( Figure 6.2.4: Sparse radix-4 carry tree.
8 6,< 79!""#"$ 3!= HD%" HD%$ "1G $M # AT/ U"1O% "1$ D#-<34!R.>/>.438 "1N "1$ "1" "1 1[ "1 1O 10 1G 1$ D#-<34!R.>/.=.-+8 1O "1 "1$ "1G "10 "1O $1 P%Q Figure 6.2.5: Output buffer and domino level converter.
9 Figure 6.2.6: Chip micrograph.
10 " c##</:.<71 0 U"1O%T/c##</:.<71 `=.-+8/P7bQ [ O V 0 M G N > ),7748/B#4:3+./!6/B3-!.> U U$1 U"1O U"10 (.3K3+./I#E.-/PµdQ M G N $ " 5G$e >#<3!= >#<3!= $ 10 1O "1 "1$ "1G "10 \ AaA(` P=6Q?3@/\-3>.5#SS/C.:E..=/>.438/3=>/.=.-+81 "1 "1$ "1G "10 "1O $1 P%Q?C@/(.3K3+./-.>,9:!#=1 Figure 6.2.7: Measured results.
IN ORDER to meet the constant demand for performance
494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004 A Shared-Well Dual-Supply-Voltage 64-bit ALU Yasuhisa Shimazaki, Member, IEEE, Radu Zlatanovici, and Borivoje Nikolić Abstract A shared
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