I/O Design EE141. Announcements. EE141-Fall 2006 Digital Integrated Circuits. Class Material. Pads + ESD Protection.

Transcription

1 EE141-Fall 2006 Digital Integrated Circuits nnouncements Homework 9 due on Thursday Lecture 26 I/O 1 2 Class Material Last lecture Timing Clock distribution Today s lecture I/O Power distribution Intro to adders Reading Chapter 11 I/O Design 3 4 Pads + ED Protection Chip Packaging PD R D1 D2 X C Diode L onding wire L Chip Lead frame Pin Mounting cavity ond wires (~25μm) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100μm in 0.25μm technology), with large pitch (100μm) Many chips areas are pad limited 5 6 1

2 Pad Frame Layout Die Photo Chip Packaging n alternative is flipchip : Pads are distributed around the chip The soldering balls are placed on pads The chip is flipped onto the package Can have many more pads 7 8 Impact of Resistance Power Distribution We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates 9 10 RI Introduced Noise I Resistance and the Power Distribution Problem efore fter pre X R V V M1 I R V Requires fast and accurate peak current prediction Heavily influenced by packaging technology 11 ource: Cadence 12 2

3 Power Distribution Power and Ground Distribution GND Low-level distribution is in Metal 1 Power has to be strapped in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects lways use multiple contacts on straps Logic Logic GND GND (a) Finger-shaped network (b) Network with multiple supply pins Metal Layer pproach (EV4) 4 Metal Layers pproach (EV5) 3rd coarse and thick metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing 4th coarse and thick metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 3 Metal 2 Metal 1 Metal 2 Metal 1 Courtesy Compaq 15 Courtesy Compaq 16 6 Metal Layer pproach EV6 Decoupling Capacitors 2 reference plane metal layers added to the technology for EV6 design olid planes dedicated to Vdd/Vss ignificantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd UPPLY oard wiring C d onding wire CHIP Metal 4 Metal 3 RP1/Vss Metal 2 Metal 1 Decoupling capacitor Decoupling capacitors are added: On the board (right under the supply pins) On the chip (under the supply straps, near large buffers) Courtesy Compaq

4 Decoupling Capacitors Under the die dders n Intel Microprocessor it-liced Design Control 9-1 Mux 5-1 Mux a CRRYGEN g Mux node1 ck1 2-1 Mux b UMGEN + LU LU : Logical Unit s0 s1 UMEL REG sum sumb to Cache Data-In Register dder hifter Multiplexer it 3 it 2 it 1 it 0 Data-Out 1000um Itanium has 6 64-bit integer execution units like this one Tile identical processing elements it-liced Datapath Itanium Integer Datapath From register files / Cache / ypass Multiplexers hifter dder stage 1 Wiring Loopback us Loopback us dder stage 2 Wiring Loopback us it slice 63 dder stage 3 it slice 2 it slice 1 it slice 0 um elect To register files / Cache 23 Fetzer, Orton, ICC

5 Full-dder The inary dder Cin Full adder um Cout Cin Full adder um Cout = = = Express um and Carry as a function of P, G, D The Ripple-Carry dder Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = ,0,0,1,2,3 F F F F (=,1 ) Worst case delay linear with the number of bits t d = O(N) Can also derive expressions for and based on D and P t adder = (N-1)t carry + t sum Note that we will be sometimes using an alternate definition for Propagate (P) = + 27 Goal: Make the fastest possible carry path circuit 28 Complementary tatic CMO Full dder Inversion Property X F F 28 Transistors

6 Minimize Critical Path by Reducing Inverting tages etter tructure: The Mirror dder Even cell Odd cell VDD,0,0,1,2,3 F F F F "0"-Propagate Kill "1"-Propagate Generate Exploit Inversion Property 24 transistors The Mirror dder The NMO and PMO chains are completely symmetrical. maximum of two series transistors can be observed in the carrygeneration circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node. The reduction of the diffusion capacitances is particularly important. The capacitance at node is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size. Next Lecture dders, Multipliers