NOVEL DESIGN OF 10T FULL ADDER WITH 180NM CMOS TECHNOLOGY

Transcription

1 International Journal of Electronics Engineering Research. ISSN Volume 9, Number 9 (2017) pp Research India Publications NOVEL DESIGN OF 10T FULL ADDER WITH 180NM CMOS TECHNOLOGY K.K.Verma 1, S.N.Shukla 2, Sanjay Kumar Jaiswal 3 and Maharishi Vaish 4 1,2,3,4 Department Physics and Electronics, Dr. Ram Manohar Lohia Avadh University, Faizabad, India. Abstract Novel design of 10T full adder circuit is proposed and qualitatively compared with 28T and 14T full adder design. Proposed 10T full adder design consumes significantly low power (~0.001 mw) and fabrication area (~276µm 2 ) than other full adder designs of its class. W/L of NMOS in the proposed design is kept 540/180 nm whereas for PMOS it is 1620/180 nm. The proposed circuit is designed and optimized using the Transmission Gate (TG) technology. Delay and power analysis of the adders under discussion are done at different Vdd. Proposed full adder design may be advantageously used in microprocessors and digital signal processing circuits. Keywords: ALU, CPU, low power, dynamic power, DSP, VLSI. INTRODUCTION Full adder is used as basic component for designing all types of microprocessor and digital signal processing (DSP) systems which determines the overall performance of the system. The scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of Digital circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems. To increase circuit performance rapidly by the scaling of sub-micron technology. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore, in realizing Modern

2 1408 K.K.Verma, S.N.Shukla, Sanjay Kumar Jaiswal and Maharishi Vaish day VLSI circuits, low-power and high-speed are the two predominant factors which need to be considered. Like any other circuits' design, the design of high-performance and low-power adders can be addressed at different levels, such as architecture, logic style, layout, and the process technology. Present investigation is an attempt to configure a full adder circuit which consumes significantly low power with reduced number of transistors. 2. DESIGN DESCRIPTION Present investigation deals with a qualitative comparison of three different logic designs of CMOS full adders that are sequentially depicted in fig.1, fig.5 and fig.9. Fig.9 accommodates schematic of proposed design whereas others are used in the discussion as reference schematics. Investigators of fig.1 and fig.5 [ref.1 & 2] initially developed respective designs of full adder with 380nm and 180nm CMOS technology. However, to provide a fair comparison environment all the logic designs under discussion are simulated herein with 180nm CMOS technology. Every logic design of full adder under discussion use equal number of PMOS and NMOS transistors. Schematics of CMOS full adders under discussion are developed by Tanner Tool (Version 13.1) whereas fabrication layout is generated by Micro Wind simulation software. 28T Full Adder The schematic of 28T CMOS full adder [ref.1] is shown in fig.1. This full adder design accommodates 28 CMOS transistors with output connected to ground through NMOS and Vdd through PMOS. Respective simulation results showing the output waveform and output power of 28T full adder design with 180nm CMOS technology are depicted in fig.2 and fig.3. However fabrication layout of the 28T full adder with 180nm CMOS technology is presented in fig.4. Fig.1: Schematic of 28T Full adder

3 NOVEL DESIGN OF 10T FULL ADDER WITH 180NM CMOS TECHNOLOGY 1409 Fig.2: Output waveform of 28T Full adder Fig.3: Output power of 28T full adder 14T Full Adder Fig.4: Layout of 28T adder The schematic of 14T CMOS full adder [ref.2] is shown in fig. 5. This adder has improved output than single logic adders. This adder has reduced number of transistors and power dissipating nodes but it has less driving capability and noise immunity. Respective simulation results showing the output waveform and output power of 14T full adder design with 180nm CMOS technology are depicted in fig.6 and fig.7. However fabrication layout of the 26T full adder with 180nm CMOS technology is presented in fig.8.

4 1410 K.K.Verma, S.N.Shukla, Sanjay Kumar Jaiswal and Maharishi Vaish Fig.5: Schematic of 14T Full adder Fig.6: Output waveform of 14T Full Adder Fig.7: Output power of 14T full adder Fig.8: Layout of 14T adder

5 NOVEL DESIGN OF 10T FULL ADDER WITH 180NM CMOS TECHNOLOGY T Full Adder The schematic of the proposed 10T CMOS full adder is shown in fig. 9. Proposed 10T CMOS full adder circuit design is optimized to consume less power and less fabrication area with lesser internal capacitance. Respective simulation results showing the output waveform and output power of 10T full adder design with 180nm CMOS technology are depicted in fig.10 and fig.11. However fabrication layout of the 26T full adder with 180nm CMOS technology is presented in fig.12. Fig.9: Schematic of 10T Full adder Fig.10: Output waveform of 10T Full Adder Fig.11: Output power of 10T full adder

6 1412 K.K.Verma, S.N.Shukla, Sanjay Kumar Jaiswal and Maharishi Vaish Fig.12: Layout of 10T adder 3. RESULTS AND DISCUSSION Simulation results of reference designs (fig.1 and fig.5) and proposed design are found to obey the conventional logic of full adder, as is depicted in Table1. Table1: Truth table of full adder Va Vb Vc Vsum Vcarry Simulation results related to the delay, fabrication area and power consumption of the circuits under discussion are represented in Table 2 and Table 3. Table 2: Power analysis for various designs Design Power (mw) at different Vdd Vdd=1.8 V Vdd=2 V Vdd=3 V Vdd=5 V 28T mw mw mw mw 14T mw mw mw mw 10T mw mw mw mw

7 NOVEL DESIGN OF 10T FULL ADDER WITH 180NM CMOS TECHNOLOGY 1413 Table 3: Delay analysis and Fabrication area for various designs Design Delay (ns) at different Vdd Fabrication Area 28T µm 2 14T µm 2 10T µm 2 Table 2 refers that power consumption for reference adder circuit of fig.1 is 0.453mW whereas it is observed 0.001mW for proposed adder of fig.9. This shows that reducing the transistors all most three times from the reference design of fig.1 records 453% reduction in power consumption for proposed adder of fig.9. Thus the purposed adder design consumes least power than other designs of reference adders at similar 180nm CMOS technology platform. This sussegests that the purposed full adder designs may be adequately useful for the ALU s of present day microprocessors and digital signal processing circuits. Simultaneously, reduced fabrication area, as represented in fig.12, is another advantageous factor with purposed design. Though the delay factor at different supply voltage (Vdd) is higher than reference adder of fig. 1 and lower than reference adder of circuit of fig.5 but this does not diminish the importance of purposed adder circuit in using preset day arithmetic logic circuits. 4. CONCLUSION In this paper, the main goal is to improve the performance of full adder such as delay for generating sum and carry and to reduce the overall power dissipated in the circuit with less number of transistors in order to reduce area. All parameters were compared with 10T, 14T and 28T adder. Due to less area, low power, and small delay 10T adder is quite useful in portable applications. Static power loss of 10T full adder is very less. So, power loss is dynamic type. REFERENCES [1] JAURA Nitasha, Balraj SINGH SINDHU and Neeraj GILL Optimization of low power adder cells using 180nm TG technology International Journal of Advanced Technology in Engineering and Science. 2014, Volume No. 02, Issue No. 10, October ISSN [2] A.Sai Ramya, Mounica ACN Performance analysis of different 8-bit full adders IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver.

8 1414 K.K.Verma, S.N.Shukla, Sanjay Kumar Jaiswal and Maharishi Vaish II (Jul - Aug. 2015), PP 35-39e-ISSN: , p-issn No. : [3] Dan Wang, Maofeng Yang, Wu Cheng, Xuguang Guan, Zhangming Zhu, Yintang Yang. Novel Low Power Full Adder Cells In 180nm CMOS Technology. ICIEA. pp [4] Radu Zlatanovici, Sean Kao, and Borivoje Nikolic. Energy Delay Optimization Of 64-bit carry- Look Ahead Adders With a 240 ps 90 nm CMOS Design Example. IEEE Journal Of Solid-State Circuits. pp [5] Sreehari Veeramachaneni, M.B. Srinivas. New Improved 1-bit Full Adder Cells. IEEE pp [6] PANDA Saradindu, Mohan Kumar, C. K. Sarkar, Transistor Count optimization Of Conventional CMOS Full Adder and Optimization Of Power And Delay Of New Implementation Of 18 Transistor Full Adder By Dual Threshold Node Design With Submicron Channel Length. International Conference On Computers And Devices For Communication, pp