EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems

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1 EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems

2 Agenda Introduction ti LP techniques in detail Challenges to low power techniques Guidelines for choosing various techniques

3 Why is Power an Issue? Leakage Power Performance = Active Power Complex System mw/mhz Source: EETimes, Process Technology (nm) Power hungry process Sluggish Battery Life Improvement Source: Intel,

4 Approaches To Power Management Leakage Active Design and System Level Optimization System Architecture (multi-core) Software/Hardware power management system ARM IEM Voltage scaling / frequency scaling Multiple voltage islands Implementation Clock gating, logic structuring We will discuss this Multi-V th cell selection to reduce leakage in detail Support for multi voltage islands (aka multi-vdd aka MSV ) implementation Signoff accurate analysis SOI Process Level Optimization High-K, Gate Stack, power gating, etc. LLD

5 Controlling Power in Implementation Dynamic power Leakage power ( k C V 2 L DD2 f CLK ) ( V DD I leakage ) Clock gating (including de-clone) Area optimization Static voltage scaling (MSV)* Dynamic voltage frequency scaling (DVFS)* Adaptive voltage scaling (AVS)* Multi-Vt cell optimization Substrate biasing (VT CMOS) Power shut-off (PSO) aka MTCMOS - including State retention Fine grain control Coarse grain control * Techniques that affect both dynamic and leakage power

6 Techniques and Trade-offs Power reduction technique Leakage power Dynamic power Timing penalty Area penalty Methodology impact Dynamic power optimization 10% 10% 0% -10% None Multi-Vt optimization 6X 0% 0% 0% Low Clock gating 0% 20% 0% <2% Low Voltage Islands 2X 40-50% 0% <10% Medium Power shut-off (PSO) 10-50X 0% 4-8% 5-15% Medium-high Dynamic and Adaptive Voltage Frequency Scaling (DVFS and AVS) 2-3X 40-70% 0% <10% High Substrate Biasing 10X - 10% <10% High Source Customer interviews, Conference papers (ISSCC), magazine articles

7 LP Techniques in Detail

8 Dynamic Power Optimization (No V) Pin swapping: low C with high F Gate sizing: CMOS power usage related to size Buffer removal: remove unnecessary buffers inst_2

9 MVT Optimization Low V t Norm V t Implementation High V t

10 Clock Gating Relies on clock gate control signal in RTL or netlist RTL clk) if (en) out <= in; Control signal Block A Maps to either: clk 1. User defined gating module Block B 2.Clock-gating-integrated cell from library clk 3.Gating function built from standard logic

11 Designing with Voltage Islands 12VPowerDomain V Power Domain clamps Low V t (High Speed) Normal V t High V t (low leakage, lower Speed) Memory Voltage Level Shifter 1.2V Domain Power Domain 3 (0.8V) Voltage Level Shifter clamps

12 Power Switch-Off (PSO) Methodologies Fine Grain Power Switches Coarse Grain Power Switches VDD VDD Real VSS Switch SLEEP A Z SLEEP Real VSS Virtual VSS (No Pin) A Virtual Vss VDD Virtual Vss Z Standard Cell Vdd SLEEP Real VSS Vdd SLEEP Real VSS Standard Cells (power switch Built-in) Standard Cells Switch Module Logical Representation (No change except for SLEEP) Logical Representation (Logic needs to be power aware!)

13 Coarse Grain PSO Methodologies Always On (Default Domain) Always On (Default Domain) On/Off Domain Always On Domain Always On Domain Global Vdd Switched VDD GND Power Switching cell On/Off Domain Cluster Switches Segmented Switches Global Vdd Separated Area VDD Common GND Power Switching cell

14 Dynamic Voltage Frequency Scaling Hardware that scales supply voltage and clock frequency in response to software demands 16 levels of VDD (use 5 to 7 in practice) from 1.1V to 0.6V Clock frequency from 200MHz to 700MHz in increments of 33MHz Triggered when load change (detected by CPU software, or HW) (load means number of functions to be executed) Heavier load ramp up supply voltage, when stable, then scale up clock frequency Lighter load scale down clock frequency, when PLL locks onto new rate, ramp down supply voltage Must keeps clock frequency within limits required by supply voltage to avoid clock skew problems, timing violation. Worst-case scenario of a full swing from 0.6 V to 1.1V and from 200MHz to 700MHz could take about 280 microseconds. En nergy/power Power Energy Characteristics of a Processor 300 Mhz, 0.80 V 433 Mhz, 0.875V 533 Mhz, 667 Mhz, 0.95 V 1.05V Operating Points 800 Mhz, 1.15V 900 Mhz, 1.25V Energy 1000 Mhz, 1.3V Source Magazine article

15 Dynamic Voltage Frequency Scaling Mode Core Sleep Slow SLEEP SLOW Baseline 1.08V 1.08V 1.08V 125MHz 125 MHz 125 MHz CORE Slow 1.08V 125MHz 1.08V 125MHz 0.9V 66MHz Standby 0.0V 1.08V 125MHz 0.0V Multiple constraints (.sdc) Example: baseline.sdc, ios.sdc, slow.sdc, sleep.sdc Libraries stdcell_1.08sl.lib, stdcell_0.9sl.lib, stdcell_1.08fs.lib, stdcell_0.9fs.lib lib Multiple modes need to be analyzed/optimized for multiple corners Setup analysis for (WC, 1,125C) corner

16 Adaptive Voltage Scaling Operating Voltage PM PM PM CPU/SOC PM Performance parameters Power Management Unit Closed loop control

17 Substrate Bias Control Vdd Vbp Vbn Vth (V) , , , 0.7-1, , , 0.45 Vss Vsb (V) For an n-channel device, the substrate is normally tied to ground (Vsb = 0) A negative bias on Vsb causes Vth to increase Substrate biasing can be done during packaging (VTCMOS) or during operation (ABB)

18 Challenges to implementing LP Techniques

19 Dynamic Power Optimization (No V) Toggle reduction Efficient synthesis Capacitance reduction Placement Physical synthesis Toggle based Capacitance reduction Pin swapping Area compaction Wire length minimization (high-toggle, fanout) Useful skew

20 MVT Optimization Library characterization ti Identical footprint Footprint independent Implementation Efficiently replacing lower V t cells with higher V t cells Analysis How/When to measure leakage power? Signal Integrity Analysis Lowest leakage state

21 Clock Gating Identifying i gating conditions Testability requirements Physical effects of clock gating Timing effects of clock gating g latch_posedge_precontrol_obs test enable ck_in ck_out obs Observability Logic... SI SO SE Specify max #flops observable per observability flop (default=36)

22 Low Power Clock Tree Synthesis De-Cloning CLK CLK Congestion! Skew! Dynamic power De-cloning CGEnable Clock Gates CGEnable Clock Gates Flip flops Flip flops

23 Voltage Islands Which logic modules are suitable for voltage scaling? What should be the scaled voltage value for these blocks? Library characterization Multiple voltages/ multiple conditions Additional components Voltage level shifters Implementation Physical shape of the voltage islands Level shifter insertion in the netlist Placement of level shifters Routing to a level shifter Power connection of a level shifter Analysis Timing analysis of islands Optimization including level shifters Signal integrity analysis IR drop and how it affects timing

24 Power Switch-Off Library Characterization Additional parameters leakage power, max. current through the cells (Id), max. voltage drop Additional cells Switches, isolation cells, state retention cells Implementation Logic level Switch insertion/simulation/verification Switch placement schemes Ring/Column/Distributed Switch enable distribution high fan out net Power planning/routing Fine grain, coarse grain SRPG control signals Analysis Transient analysis On/Off analysis Functional verification Sneak path analysis

25 DVFS/AVS Library characterization ti Advanced modeling (ECSM, CCS) Implementation Clock synchronization Use of level shifters in the clock design Analysis Multi-mode/multi-corner analysis/optimization Functional verification (huge for AVS)

26 Substrate Bias Timing Analysis Characterization for VTCMOS Custom analysis for ABB Optimization Must be aware of body bias Well separation Between the regions that are subjected to control and that are not Planning/routing additional power signals Congestion EM Cell design Functional Verification/validation

27 Variability and Low Power Test Chip Timing Path Slack Distribution, -100ps -> +200ps 16% notime ths % of pa 14% 12% 10% 8% 6% 4% 2% timed MVT MSV 0% ps

28 Functional Checks Need to be Transistor Level VDD VDD PwrEn1 PwrEn2 Power Control FSM PwrEn1 PwrEn2 ISO A V1 A Vs Vc Y B V2 A Vs Vc Y ISO ISO Iso Level Shifting Isolation Cell in Source Domain, which will be shut off

29 State Retention Register Checks PwrEn1 SW A Power Controller PwrEn1 RTCLK RET ON/OFF V 1 D RET VDD VRET SRPG Q V 2 RTCLK RTCLK Don t care D Don t care Q RET Sleep X Wake Structural ral Check Checks that RET signal comes from an Always ON power domain; VRET tied to continuous Power Checks that VDD and D pins connect to the same power domain Functional Checks assert (RET RET ) (RTCLK off)

30 Sneak Path Detection Floating node when X is switched-off can cause additional leakage ENB VDD Block X A Y EN VSS Common in mux logic

31 Guidelines for LP Technique Selection

32 How To Choose Between Various LP Techniques Understand the application/technology need for power reduction Choose the techniques based on the power reduction requirement and not vice versa. Understand the trade-offs esp. methodology implications

33 High-level Guidelines for Power Reduction in Design Power is a performance parameter similar il to area and timingi Optimize and analyze timing, power and area concurrently Choose the LP techniques early in the implementation Helps to get max. power reduction Architecture/process selection must be driven by power need Use of voltage scaling techniques leads to quadratic reduction in power e.g. MSV, DVFS When not in use, shut it off! Verify, verify, verify!

34 Steps for Successful LP Design Tapeout! LP implementation is complex and requires more time (2X) than normal. Plan ahead! Library characterization can time consuming as new cells need to be designed and the existing cells characterized under new conditions. Choose a comprehensive implementation tool to address not only a range of techniques, but also trade-offs between power, area and timing. LP techniques force you to change the existing methodology adding new tools and steps. In order to be successful, consider partnering with a EDA vendor (Cadence!) Verification is key to successful implementation. Make sure the verification tool can understand low power techniques.

35 Backup

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