CHAPTER 1 INTRODUCTION

Transcription

1 CHAPTER 1 INTRODUCTION

2 2 1.1 MOTIVATION FOR LOW POWER CIRCUIT DESIGN Low power circuit design has emerged as a principal theme in today s electronics industry. In the past, major concerns among researchers and designers for designing integrated circuits were on area, speed, and cost; while secondary importance was paid to power dissipation. In recent years, however, this scenario has changed and now developing of different circuit techniques for low power circuit design is an important research area. For long, low power circuit design was only used by circuit designers in specific areas, such as medical electronic implant where low power dissipation was a crucial factor. Low power circuit design has now become a subject of interest, which is evident from the surge of related activities in the engineering and research community. Several factors have contributed to this trend. The primary driving factor behind low power circuit design is the remarkable growth and success of portable systems that are driven by batteries. In these systems, low power dissipation is a critical design concern. Limited amounts of energy stored in portable batteries require extensive power management techniques to increase their lifetime. Battery life is becoming a product differentiator in battery operated portable electronic systems. Being the heaviest and the biggest component in many portable systems, batteries have not experienced the similar rapid density growth as compared to the growth in electronic devices. The specific weight (stored energy per unit weight) of batteries barely doubles in several years. Besides technological issues, further increase in battery specific weight will soon draw safety concerns because the energy density is approaching to that of explosive chemicals. With advanced nickel-metal-hydride (secondary) battery technology, offering around 65 watt hour/kilogram, an unacceptable 6 kilograms of battery would be required for 10 hours of operation between recharges (Kohler et al. 2002). Even with new battery technologies, such as rechargeable lithium ion or lithium polymer cells, there would not be too much improvement in the expected battery lifetime. With the increasing demand for battery operated portable systems, it is important to increase the battery lifetime as much as possible, since it is the limited battery lifetime that typically imposes strict restrictions on the overall power dissipation in such systems. Although, the battery industry has been making efforts to develop portable batteries with a higher energy capacity, a revolutionary increase in the energy capacity does not seem imminent. In the absence of effective low power circuit design

3 3 techniques, present and future portable systems will either suffer from very short battery life or very heavy battery pack. So, portable systems that are powered with battery require low power circuit design to minimize the drainage of battery power for increasing the battery lifetime. Low power circuit design is highly desirable for burst mode type system, where computation occurs for only short intervals, and the system is inactive for the majority of time. For such type of battery operated systems, it is highly unacceptable to have excessive drainage of useful battery power during the long standby period. So, low power circuit design is also essential for these battery operated systems to reduce the excessive drainage of battery power during the long idle period. To further improve the performance and to integrate more functions on a chip, the feature size of a MOS transistor continues to shrink. As a result, the power dissipation per unit chip area also increases, which in turn increases the chip temperature. The usual scaling trends in MOS transistors are facing problems due to the extreme rise in the device temperature (Borkar 2002). With clock speed exceeding several GHz and switching millions of transistors, chip temperature has reached at such an alarming level that requires expensive packaging and efficient system cooling techniques to decrease the system temperature (Bursky 1995). Fig. 1.1 shows an increase in power density of Intel processors with the advancement in technology generation, year after year (Borkar 2002, Esmaeilzadeh et al. 2013). Power densities of high performance chips have also increased significantly over the last twenty years. The increased power dissipation and power density in electronic systems lead to higher operating system temperature. This high power dissipation requires special printed circuit board technology to deliver large currents from the power supply to various devices in the system. Since the dissipated heat needs to be removed to maintain an acceptable chip temperature, so expensive system cooling and packaging techniques are required in portable and high performance systems, such as microprocessors. This increases the overall cost of the system. So, low power circuit design is becoming an essential criterion in designing an energy efficient system.

4 4 Fig.1.1 Power density of Intel processors In addition to cost, the issue of reliability in an electronic system also motivates for low power circuit design. High power dissipation systems often run hot, and the high temperature tends to accelerate the silicon failure mechanism. Every 10 o C increase in the operating temperature roughly doubles an electronic component s failure rate (Charles 1994). With the down scaling in technology, the power density of a system increases, which also increases its current density. Large current densities can cause serious problems such as electromigration and hot carrier induced device degradation (Quader et al. 1994). In addition, the heat gradient across the chip also causes thermal and mechanical stress, leading to device breakdown. Serious reliability issues arise in electronic systems at such high temperatures. Therefore, the reliability of a system can only be enhanced if the power dissipation by the system is reduced by adopting effective low power circuit design techniques. Another major demand for low power circuit design comes from environmental concerns. Modern offices are now furnished with office automation equipments that consume large amount of power. Computers are the fastest growing electricity loads in commercial sector. Since electricity generation is a major source of air pollution, so inefficient energy usage by computing equipments indirectly contribute to an increase in the environmental pollution (Yeap 1988). This problem has prompted the environmental protection agencies to promote the energy star program that sets guidelines for the energy usage by various computing equipments (Murugesan 2008). This trend has led to the development of the concept of green computers, which consume lower power, and

5 5 are therefore environmental friendly. Emerging policies that work for a low environmental impact from electronic systems also encourage low power circuit design. Today, many desktop computers, monitors and printers have been certified as energy star compliant. Consequently, reducing the power dissipation by utilizing low power circuit design is becoming a top priority issue. The motivation for low power circuit design differs from applications to applications. In case of battery operated portable systems, such as cellular phones and laptops, the overall goal of power minimization using low power circuit design is to keep the battery lifetime and weight reasonable. For high performance and non battery operated systems, such as workstations and multimedia digital signal processors, the overall goal of power minimization is to reduce the overall system cost (cooling, packaging and energy bill) while ensuring long term device reliability. These different requirements are the motivating factors for low power circuit design in electronic systems. 1.2 BACKGROUND Reducing power dissipation has now become a critical design concern in almost all electronic systems. Reduction in the supply voltage is the most significant method for reducing the power dissipation because of the quadratic relationship between the supply voltage and the dynamic power dissipation (Wang et al. 2012). To compensate for the performance loss due to a lower supply voltage, threshold voltage of MOS transistors is also reduced. However, this causes an increase in the leakage current. Among all leakage currents, subthreshold leakage current is the most dominant (Deepaksubramanyan et al. 2007). This leakage current will become a large component in the total power dissipation with further down scaling in technology. Therefore, today an important research area in achieving low power dissipation is to develop effective circuit techniques to reduce this leakage current that is mainly caused by the reduction in the threshold voltage of MOS transistors and down scaling in technology (Roy et al. 2003). Technology scaling has allowed more functions per unit area, and lower dynamic power dissipation, but has also increased the leakage power dissipation exponentially. An analysis of trends based on the International Technology Roadmap for Semiconductors (ITRS) shows that the leakage power dissipation is beginning to

6 6 exceed the dynamic power dissipation with the down scaling in technology generation, which is shown in Fig. 1.2 (Elgharbawy et al. 2005, Calhoun et al. 2009). In the past, circuit design techniques and architectures ignored the effects of leakage power dissipation because it was insignificant in comparison with the dynamic power dissipation. However, in modern technologies, the role of subthreshold leakage power dissipation cannot be ignored and now it has become dominant in the overall power dissipation in deep submicron and nanoscale technologies (Roy et al. 2003). Fig. 1.2 Leakage versus dynamic power dissipation trends with technology scaling Fig. 1.3 shows the power dissipation in standard CMOS circuits using long channel MOS transistors without scaling in the supply and threshold voltage. Fig. 1.4 demonstrates the increase in the standby leakage power dissipation in standard CMOS circuits using short channel MOS transistors. This demonstrate that the increase in the standby leakage power with technology scaling due to the use of short channel MOS transistors completely cancels the benefit of reduced dynamic and leakage power in active mode with the reduction in the supply voltage (Anis et al. 2010). Although total power dissipation (dynamic and leakage) during the active mode is reduced with the scaling in the supply voltage, further power dissipation can only be reduced if standby leakage power dissipation is controlled wherever possible, since this leakage power will make up a larger percentage in the overall power dissipation with further

7 7 scaling down in technology. Fig. 1.5 shows reduction in power dissipation in standard CMOS circuits using short channel MOS transistors with supply and threshold voltage scaling and using improved standby leakage reduction techniques. During long idle or standby period, when no computation is taking place, the standby power dissipation tends to increase further since leakage currents are large. So, low power design methodologies used in the past, based on dynamic power considerations only, are not effective anymore and need to be reconsidered. Fig. 1.3 Power dissipation in standard CMOS circuits using long channel MOS transistors without supply and threshold voltage scaling Fig. 1.4 Power dissipation in standard CMOS circuits using short channel MOS transistors with supply and threshold voltage scaling Fig. 1.5 Power dissipation in standard CMOS circuits using short channel MOS transistors with supply and threshold voltage scaling and using improved standby leakage reduction techniques

8 8 For systems that have long idle or standby period, such as personal digital assistants, cell phones, and wireless sensor network nodes, subthreshold leakage power dissipation in the standby mode is highly undesirable. The impact of standby leakage power is more evident for systems that have a low activity factor and remain in idle or standby state for the majority of time. Standby leakage power becomes a large percentage of the total power dissipation in these systems. These systems approximately spend more than 90% of their time in the standby mode (Hirabayashi et al. 2001). Thus, a large percentage of the total power is wasted in the standby period. Fig. 1.6 shows savings factor curve for a 5% duty cycle system with the down scaling in technology (Anis et al. 2010). For this system, 20x savings factor is significantly degraded each year with the scaling down in technology generation. Burst mode type systems are a class of low duty cycle systems, where most of the activity is naturally grouped together in time frame. These systems are also known as event driven systems, where a burst of activity occurs in response to an input event, and the system is otherwise idle. Some examples of burst mode type systems are sensor network nodes, personal digital assistants (PDAs), and cell phones. In case of a sensor network node, the system is usually waiting for a new data packet, a periodic sensor reading, or user input. When one of these events occurs, the node processes it for completion and then waits for the next one. Similarly most of signal processing processors in cell phones remain in the idle state until a call is being made or received. For this class of burst mode type system, it is extremely wasteful to have a large leakage current during the idle or standby period because no useful works are being done during this period. This problem is especially severe for portable battery operated burst mode type systems, where battery power is needlessly drained during the long idle period. So, this standby leakage power dissipation should be reduced significantly by using effective standby subthreshold leakage control techniques.

9 9 Fig. 1.6 Savings factor curve for a 5% duty cycle system The most commonly used subthreshold leakage reduction techniques available in the literature are source biasing technique (Bellaouar et al. 1995), stack technique (Johnson et al. 2002), dual V TH partitioning technique (Hirabayashi et al. 2001), variable threshold CMOS (VTCMOS) technique (Hyunsik et al. 2001), sleepy keeper technique (Kim et al. 2006), multi-threshold CMOS (MTCMOS) technique (Mutoh et al. 1995), and super cutoff CMOS (SCCMOS) technique (Kawaguchi et al. 2000). Out of these techniques, MTCMOS technique, and SCCMOS technique are mostly used for reducing the standby subthreshold leakage power dissipation. In MTCMOS technique, high threshold voltage MOS transistors are used to disconnect the power supply and the ground during the standby period, which substantially reduces the standby leakage power. However, in this technique circuit delay is increased by the use of high threshold voltage MOS transistors. The main advantage of SCCMOS technique over MTCMOS technique is the reduction in the circuit delay due to the use of low V TH sleep MOS transistors. However, in SCCMOS technique, a complex controller circuit is used for providing both negative and positive gate voltages to completely turn off sleep nmos and sleep pmos transistors respectively. Existing standby subthreshold leakage reduction techniques, such as MTCMOS technique and SCCMOS technique, still suffer from higher standby subthreshold leakage power dissipation, which can aggregate to a larger amount of power wastage during the long idle period, especially in burst mode

10 10 type systems. Hence, there is a great need for improved circuit techniques for further minimizing this standby leakage power dissipation for saving useful battery power in the standby period. 1.3 RESEARCH OBJECTIVES The main objective of this thesis is to design low power digital circuits in deep submicron and nanoscale technologies by effectively reducing the standby subthreshold leakage power dissipation. The research work presented in this thesis offers a set of novel and improved standby subthreshold leakage reduction techniques by utilizing proper selection of low power design methodologies at the transistor and circuit levels of abstraction. In this thesis, main focus is given on further reduction of this standby leakage power dissipation since this leakage power contributes a larger percentage in the overall power dissipation with further down scaling in technology, especially in burst mode type systems. Literature survey reveals that a wide variety of circuit techniques (Bellaouar et al. 1995, Johnson et al. 2002, Hirabayashi et al. 2001, Hyunsik et al. 2001, Kim et al. 2006, Mutoh et al. 1995, Kawaguchi et al. 2000) are available for reducing the subthreshold leakage power dissipation. However, MTCMOS technique (Mutoh et al. 1995) and SCCMOS technique (Kawaguchi et al. 2000) are the major existing techniques that are mainly used for reducing the standby subthreshold leakage power. Existing standby subthreshold leakage control techniques still dissipate a larger leakage power in the standby mode. Study of literature reveals that there is still further scope for designing improved standby subthreshold leakage control techniques, which can further reduce this standby power. Hence, these existing techniques have to be suitably modified by selecting proper low power design methodologies for further reducing this leakage power dissipation. Burst mode type systems that are driven by portable batteries are heavily affected by the standby leakage power because these systems remain in the standby state for the majority of time interval. In these systems, useful battery power is drained out during the long standby period. So, there is a great need for improved circuit technique to further reduce and minimize this standby subthreshold leakage power dissipation so that the battery lifetime can be increased significantly. The drainage of

11 11 battery power during the long standby period can be effectively minimized, after proper and effective reduction of this standby leakage power dissipation. This thesis is the record of some new and efficient circuit techniques for proper and effective reduction of the standby subthreshold leakage power dissipation.the proposed circuit techniques are based on CMOS bulk technology and advanced siliconon-insulator (SOI) CMOS technology. The suitability of the proposed circuit techniques are validated through layout design and simulation of different digital circuits using BSIM4 MOS parameter model. Layout design and simulation of various digital circuits using the proposed and existing standby subthreshold leakage control techniques are performed by using Microwind ver. 3.1 EDA tool. Existing standby leakage control techniques are compared with the proposed techniques in terms of dissipating the least standby leakage power dissipation. This thesis focuses on circuit level techniques to handle the exponentially increased standby subthreshold leakage power dissipation that is mainly caused by the down scaling in technology and reduction in the threshold voltage of MOS transistors. It is found that by utilizing novel and improved circuit techniques, this standby leakage power dissipation can be further reduced. 1.4 THESIS OVERVIEW This thesis presents new and improved circuit design techniques for effective reduction of the standby subthreshold leakage power dissipation. The main content of the dissertation is divided into eight chapters. Chapter 1 describes about the motivation for low power circuit design. This chapter also describes about the background and research objectives for low power circuit design, with more emphasis on minimizing the standby subthreshold leakage power dissipation. Among all the leakage currents, subthreshold leakage current is the dominant source of leakage power dissipation. So, by using effective standby leakage control techniques, leakage power in the standby mode can be reduced further. Finally, organization of the thesis is presented. In chapter 2, main sources of power dissipation in digital logic circuits are reviewed, with more emphasis on the subthreshold leakage power. The increasing impact of standby subthreshold leakage power dissipation with the down scaling in technology is then presented. Existing circuit techniques on controlling this standby

12 12 subthreshold leakage power dissipation is discussed in detail in this chapter. Finally, conclusion is provided at the end of this chapter. The contributions of this research work are presented in chapters 3 to 6. In chapter 3, performance of a two input NAND gate using various existing subthreshold leakage control techniques are analyzed. Static power dissipation and static power dissipation reduction factor for a two input NAND gate are compared using existing subthreshold leakage control techniques in 45nm CMOS technology. In the end, conclusion is provided. Chapter 4 presents new hybrid circuit design techniques in CMOS bulk technology for controlling the standby subthreshold leakage power dissipation. Methodologies adopted for designing the proposed circuit techniques are discussed in detail. The suitability of the proposed circuit techniques is validated through layout design and simulation of a two input AND gate in 65nm CMOS technology. Existing standby subthreshold leakage control techniques, such as MTCMOS technique, and SCCMOS technique are compared with proposed circuit techniques in terms of dissipation of standby subthreshold leakage power. It is found that the proposed technique gives better results than the previous techniques. Conclusion is provided at the end of this chapter. Chapter 5 presents another novel circuit technique in CMOS bulk technology for reduction of the standby subthreshold leakage power dissipation. Circuit design methodologies for designing this proposed technique are described in detail. Layout design of digital logic circuits such as a two input XOR gate, a two input XNOR gate, a four input XNOR gate, and a four bit ALU are simulated using the proposed and existing techniques in 45nm CMOS technology. The suitability of proposed technique is justified by comparing with other existing techniques in terms of dissipation of standby subthreshold leakage power dissipation. In chapter 6, an improved silicon-on-insulator (SOI) CMOS technology based circuit technique for effectively reducing the standby subthreshold leakage power dissipation is presented. Methodologies adopted to design this proposed technique are described in this chapter. The proposed circuit technique is validated through layout design and simulation of a one bit full adder circuit in 120nm SOI CMOS technology. Simulation results and observations using the proposed and existing techniques are

13 13 discussed in this chapter. The proposed SOI CMOS technology based circuit technique provides an effective and efficient solution for further reduction of the standby subthreshold leakage power dissipation. Chapter 7 presents comparison of popular existing circuit techniques with the proposed circuit techniques (hybrid MTCMOS complete stack technique, hybrid MTCMOS partial stack technique, hybrid SCCMOS complete stack technique, hybrid SCCMOS partial stack technique, a novel circuit technique, and an improved SOI CMOS technology based circuit technique) in terms of standby subthreshold leakage power dissipation. It is observed that the proposed improved SOI CMOS technology based circuit technique dissipates the least subthreshold leakage power in the standby mode in comparison with other proposed and existing circuit techniques in CMOS bulk technology. In chapter 8, entire results and observations of the thesis are summarized and critically reviewed.