Design of the Power Delivery System for Next Generation Gigahertz Packages

Transcription

1 Design of the Power Delivery System for Next Generation Gigahertz Packages Madhavan Swaminathan Professor School of Electrical and Computer Engg. Packaging Research Center

2 Outline What is Power Supply Noise (PSN)? Impact of PSN on Systems Basic Physics Design Tools New Technologies Summary

3 Power Supply Noise CORE CIRCUITS I/O CIRCUITS Transient current through inductors cause voltage fluctuations across the Vdd and Gnd terminals of the circuit V = L di dt

4 Impact of PSN on Systems Reduction in Power Supply Tolerance increases operating frequency This effect is pronounced for sub-micron CMOS with low voltage levels and high operating frequencies (ITRS) Effect of package and board on power supply noise can be large Chip Package Co-design techniques are therefore required to limit noise in future systems Ref: A. Waizman and C. Y. Chung, Package Capacitors Impact on Microprocessor Maximum Operating Frequency, ECTC, Orlando, Florida, May 2001

5 Basic Physics

6 Power Distribution Network (PDN) PDN for AMD Processor Equivalent Circuit

7 Frequency Response of Package and Board PDN VRM Low Frequency Caps Mid Frequency Caps Power Planes Target Impedance Low Impedance Broad Band Network Power Planes dominate response Courtesy, Larry Smith, SUN Microsystems

8 Target Impedance Courtesy, Larry Smith, SUN Microsystems

9 International Technology Roadmap on Semiconductors Max. Voltage (V) Power (W) On-Chip Clock (GHz) * Off-Chip Clock (GHz) Based on 1999 International Technology Roadmap for Semiconductors - High Performance What is the impact of the Frequency on the PDN?

10 On-Chip Power Distribution Network Clock Distribution Produces a cylindrical electromagnetic wave Attenuated Wave Low Q Circuit 90% of energy diminished within 1.2mm 4 Metal Levels with 0.25um technology Top View of PDN

11 Package Power Planes (0.5,4.5) (0.5,5.5) (5,5) Produces a cylindrical electromagnetic wave Low Attenuation High Q Circuit 99% of energy reaches the edge, reflects and produces standing waves Two unloaded power planes

12 Frequency Response of Power Planes L-Shaped Power Planes used in SUN Workstations

13 Frequency Response of Power Planes Trans-Impedance Self Impedance First resonance at 500MHz First resonance at 500MHz Inductive at High frequencies 1 mil FR4 dielectric Copper for Conductor with 1.2 mil Port 1 = (3.19",2.68") Port 2 =(3.63",2.33")

14 Transient Response of Power Planes IFFT from the frequency data Open Termination - (RS=open) (RL=open) Period = 1/(1st fmax) = 2 ns 25 clock pulses with 0.25 ns of rise and fall time Source Current at Port 1 Current Time

15 Voltage Transient Response of Power Planes Builds Energy Reaches Steady State Dissipates Energy Takes 50ns to decay to zero Time

16 Loading of Power Planes with Capacitors Self Resonant Frequency Impedance Frequency Z = R + jωl + 1 jωc Ninety seven (7 kinds) added to power planes

17 Frequency and Transient Response of Power Planes with Capacitors Self Impedance Transient Response Reduction in Impedance Reduction in Noise 500MHz Source - 25 Cycles

18 I/O Noise due to Return Currents 5V Low to High Transition Ron1 Ron2 Vdd1 Forward Current on Microstrip Return Current on Reference Plane Quiet Power Supply Gnd1 5V High to Low Transition Ron1 Ron2 Vdd1 Return Current on Reference Plane Noisy Power Supply Gnd1 Current Source Radial Wave

19 Design Tools

20 Georgia Tech Design Tools Cadence Framework Chip Circuit FDTD Patent TBD Package/Board Transmission Matrix Patents 1 & 2 Macro-modeling Patent 3 Georgia Tech Tools Non-linear Circuits Spice

21 Transmission Matrix Method Property in power/ground planes * quasi-static models * distributed & repeated T-matrix method for a plane pair * a column of unit cells * multi-input/output transfer function C 2 w 2 πfµ o = ε oε r L = µ od Rdc = Rac = 2 ( 1 + j ) Gd = ωc tan( δ ) d σ t σ c c T model Π model

22 Application of T-Matrix T Method * Motorola Bravo Plus Pager * 200 um FR-4 dielectric * 20 um copper

23 Rambus 3.2Gb/s Yellowstone Channel Switching of Transmission Lines

24 Cross section (Revisited) Focus of Modeling Top Via Gnd2 Vdd_1.2V Switching of Transmission Lines Vdd_5V Gnd5 Bottom

25 Layer 1_2_3 with 48 Capacitors No Pad Inductance for the Capacitors Master_1.2V Slave_1.2V Port 1 VRM High Speed I/O High Speed I/O Port 2,3,4,5 Port 6,7,8,9

26 Input Impedance Master_1.2V Slave_1.2V Z11 (looking from VRM) VRM 12 decaps in parallel High Speed I/O Z22 Z99 Looking from Chip High Speed I/O

27 Transfer Impedance between Master & Slave Coupling Transfer Impedance Z26,Z27..Z59 Coupling Between Master and Slave 5nH 0.02Ω/12 61pF 0.55nH/12 100nF*12 5nH 0.02Ω/ nH/12 100nF*12 Frequency

28 50 ohms Modeling of Power Supply Noise Yellowstone Channel (300mV Swing) Port 1 1.2V (Vdd) Gnd Port 2 Port 3 PDN Macro-model 1.2V (Vterm) 50 ohm Differential Driver Gnd Gnd 4 Differential Transmission Lines (50 ohms) (Vterm is assumed to be a clean supply) (Driver model used is a time dependent current switch)

29 Differential Drivers (Current Switch) Yellowstone Channel Data (Period=1.25ns, tr=0.05ns, tf=0.05ns, Tline = 50 ohms; 1ns) Data Pattern: Note: 10ps of skew introduced between the two current switches Power Supply Noise = 10mV (3 Differential Drivers)

30 New Technologies

31 Progress in Electronic Packaging Wire bond Peripheral lead Chip Chip Package Package Board Board Less vertical inductance - Thousands of C4s at 50 ph/c4 - Thousands of Solder Balls at 250pH/Solder Ball - Thousands of vias all in parallel - Vertical inductance has been minimized High Frequency Response Dominated by Planes So, where do we go from here?

32 Powering the Core Circuits of the Microprocessor Power Distribution using Multi-layered Package for Sun s 750 MHz Processor Chip Chip Circuit Load 57 mohm for 35 Amps (70 Watts) 133 mohm for 15 Amps 1.3 mohm 356 nf Inductance 0.3 mohm 102 nf 1.73 mohm Package 9 ph VRM PCB 0.18 mohm Bunch of Capacitors 0.09 mohm12.5 ph Vdd Plane Gnd Plane Port 1 Port 2

33 Frequency Response of Package Low Pass Filter Extend to higher frequencies Using Wafer Level Package Package acts as Low Pass Filter Limits the maximum operating frequency Becomes inductive at high frequencies (250MHz for PWB)

34 Wafer Level Package on High Density Integrated Board On-Chip Capacitance N-WLP Option 2 Power Supply Board resistance and Inductance from VRM Substrate Power Supply Option 1 WLP Resistance and Inductance Board Capacitors

35 Wafer Level Package on Board Core Power Distribution Frequency Response looking from chip into WLP and Board On-chip Capacitor Package Chip WLP Resonance Total Response WLP Leads Preliminary Results

36 Summary With the trend towards low voltage swings and high data rates, power supply noise is a major bottleneck Generated on Chip, Package and Board. The interactions between the three become very important Major contributor in the board are power planes Future packaging technologies need an integrated solution with the first level package eliminated