Ensuring Signal and Power Integrity for High-Speed Digital Systems

Size: px
Start display at page:

Download "Ensuring Signal and Power Integrity for High-Speed Digital Systems"

Transcription

1 Ensuring Signal and Power Integrity for High-Speed Digital Systems An EMC Perspective Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg (TUHH) Invited Presentation at the IEEE International Conference on Consumer Electronics (ICCE), Berlin, September 6-9, 2015

2 Abstract With increasing data rates and reduced margin for communication errors both consumer electronic products as well a large-scale digital systems like data centers have to be designed very carefully with respect to their electrical integrity. In this presentation two aspects of this integrity, namely signal integrity (SI) and power integrity (PI), will be explained in some detail. The focus will be put mostly on packaging and electromagnetic compatibility (EMC) aspects. Topics that will be addressed include discontinuities, transmission line effects, crosstalk, bypassing and decoupling, via and power plane effects, return current issues, and measurement techniques. The presentation should be suitable for both a technical and a non-technical audience. For more information on SI and PI research at TUHH visit: C. Schuster, TUHH 2

3 Outline (1) Motivation (2) SI, PI & EMI (3) High-Speed Digital Systems (4) Improving SI (5) Improving PI (6) Wrapping Up C. Schuster, TUHH 3

4 (1) Motivation C. Schuster, TUHH 4

5 Digital Link Data Rates Data Rate [Gb/s] 10 Infiniband 10.0 DDR G Ethernet PCIe 5.0 Hyper Transport 5.2 SATA III 6.0 SA-SCSI 3.0 Fibre Channel 4.25 DVI 3.7 USB FireWire up 3.2 CPU to CPU Storage Network/ Peripherals C. Schuster, TUHH 5

6 Digital Link Frequency Trends C. Schuster, TUHH 6

7 (2) SI, PI & EMI C. Schuster, TUHH 7

8 Digital Link Seen From.. Driver Via PCB Power Plane Ground Plane DC Power Supply Receiver C. Schuster, TUHH 8

9 .. a Signal Transmission Perspective Signal Transmission Issues: Attenuation, Reflection, Dispersion, Interference, Crosstalk C. Schuster, TUHH 9

10 .. a Signal Transmission Perspective Signal Transmission Issues: Attenuation, Reflection, Dispersion, Interference, Crosstalk C. Schuster, TUHH 10

11 .. a Power Delivery Perspective Power Delivery Issues: Voltage Drop, Switching Noise, Crosstalk C. Schuster, TUHH 11

12 .. a Power Delivery Perspective Power Delivery Issues: Voltage Drop, Switching Noise, Crosstalk C. Schuster, TUHH 12

13 .. an EMI Perspective Electromagnetic Interference Issues: Near Field Coupling, Radiated Emissions C. Schuster, TUHH 13

14 .. an EMI Perspective Electromagnetic Interference Issues: Near Field Coupling, Radiated Emissions C. Schuster, TUHH 14

15 SI + PI + EMI = Comprehensive EMC Elements of a comprehensive EMC C. Schuster, TUHH 15

16 SI/PI Foundations and Resources Circuit Design & Simulation Antenna Theory Communication Theory Numerical Techniques HF Measurement Techniques Coupler & Filter Design Transmission Line Theory SI / PI EM Field Theory Electromagnetic Compatibility Network Theory CAD Tools System Theory Material Characterizationj C. Schuster, TUHH 16

17 SI/PI Foundations and Resources C. Schuster, TUHH C. Schuster, TUHH 17 Figures C. Schuster, TET, TUHH

18 SI/PI in the IEEE Community Number of publications found in IEEE Xplore containing the index terms: Signal Integrity Power Integrity C. Schuster, TUHH 18

19 SI/PI in the EMC Community C. Schuster, TUHH 19

20 SI/PI in the EMC Community C. Schuster, TUHH 20

21 (3) High-Speed Digital Systems C. Schuster, TUHH 21

22 Daughtercard A High-Speed Digital System Housing / Chassis Cable IC (Transmitter) Package / Module Connector IC (Receiver) Connector Socket Backplane / Motherboard C. Schuster, TUHH 22

23 The SI Challenge Interconnect (Link) Connector C. Schuster, TUHH 23

24 Effect of Interconnects The ideal interconnect will simply delay the signal: Tx Rx Any real interconnect will additionally change timing and amplitude: t Tx Rx t C. Schuster, TUHH 24

25 Jitter and Noise The deviations in timing and amplitude are in general called: t Timing jitter or simply: JITTER Amplitude noise or simply: NOISE C. Schuster, TUHH 25

26 Jitter and Noise In the eye diagram timing jitter and anplitude noise are defined as follows: NOISE JITTER Receiver Sampling Point C. Schuster, TUHH 26

27 The PI Challenge 1 V 3.3 V VRM Connector C. Schuster, TUHH 27

28 Effect of Common Power Delivery Z PDN IC #1 IC #2 U 0 PDN = Power Delivery Network C. Schuster, TUHH 28

29 Effect of Common Power Delivery R L u IC U 0 Du i Gate1, i Gate2, u IC = U 0 - Du d Du( t) R Gate1 Gate1 Gate1 Gate1 dt i ( t) i ( t)... L i ( t) i ( t)... "DC-drop or IR-drop" "DI-drop or DI-noise" C. Schuster, TUHH 29

30 (4) Improving SI C. Schuster, TUHH 30

31 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce Coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 31

32 Typical Digital Link Design Data.. Interconnect Equalizer + Slicer.. Data.. Equalizer Serializer CDR Deserializer Tx Clock Clock & Data Recovery Rx High performance digital links are mostly serial: HSS = HIGH SPEED SERIAL. The technology is typically CMOS with the links being voltage mode, unidirectional, serial, point-to-point, and source-synchronous. Both single-ended and differential signaling can be found. For improved bandwidth equalization is typically used in the Tx, Rx, or both. C. Schuster, TUHH 32

33 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce Coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 33

34 Effect of Terminations Let s use the following interconnect (link) model: Z 0,, l Z S Z L?? u 0 u 1 u 2 Transmitter Interconnect Receiver C. Schuster, TUHH 34

35 Transmission Lines in Digital Systems Microstrip Line Z r ln 5.98h 0.8 w t (h = height of dielectric, w = conductor width, t = conductor thickness) Stripline (symmetric) Z 0 60 r ln 1.9 h 0.8 w t (h = height of dielectric, w = conductor width, t = conductor thickness) Metal Dielectric C. Schuster, TUHH 35

36 Effect of Terminations Let s use the following interconnect (link) model: Z 0,, l Z S Z L?? u 0 u 1 u 2 u u 2 const. and max.! 0 C. Schuster, TUHH 36

37 Effect of Terminations Z 0,, l Z S Z L input acceptance source transmission source reflection TL transfer function load transmission load reflection C. Schuster, TUHH 37

38 C. Schuster, TUHH 38 l Z,, 0 Z L Z S Effect of Terminations!! 1 ) (1 1 S L 2 L S L 2 L 0 trans 0 2 r r H r H a r r H t H a u u u u

39 Effect of Terminations Z 0,, l Z S Z L Z L Z 0 u u 2 0 a H Z S Z L Z 0 u u H C. Schuster, TUHH 39

40 Voltage Voltage Matched interconnect: Effect of Terminations lossless transmisson line lossy transmisson line Time Mismatched Interconnect: T D low source impedance 2T D high source impedance Time C. Schuster, TUHH 40

41 Effect of Terminations 1 Z S 10Ω, Z 0 50Ω, Z L 1kΩ zero losses 2 Z S 50Ω, Z 0 50Ω, Z L 100Ω zero losses 1 3 Z S 50Ω, Z 0 50Ω, Z L 50Ω zero losses Z S 100Ω, Z 0 50Ω, Z L 100Ω zero losses Z S 10Ω, Z 0 50Ω, Z L non-zero losses 1kΩ 6 Z S 50Ω, Z 0 50Ω, Z L 50Ω non-zero losses (all lines have a delay of 0.1 ns) C. Schuster, TUHH 41

42 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 42

43 Packaging of Digital Systems Interconnect (Link) Connector C. Schuster, TUHH 43

44 Effect of Lumped Discontinuities Signal In C. Schuster, TUHH Signal Out Source Voltage u 1 50 u nh 2 Received Voltage Tx-Output Bond Wire Rx-Input C. Schuster, TUHH 44

45 Effect of Lumped Discontinuities u 2 (t) / u 1 (t) Attenuation of high frequency signal components Slowing down" of the edges of a digital signal Frequency Response Step Response Magnitude of u 2 / u 1 f GHz t 1/w 0 = 25 ps Frequency [GHz] Time [ps] C. Schuster, TUHH 45

46 Effect of Lumped Discontinuities Signal In Signal Out Y. Kwark, IBM Source Voltage 50 u 1 1 pf 50 u 2 Received Voltage Tx-Output Via Rx-Input C. Schuster, TUHH 46

47 Effect of Lumped Discontinuities Attenuation of high frequency signal components!! u 2 (t) / u 1 (t) Slowing down" of the edges of a digital signal!! Frequency Response Step Response Magnitude of u 2 / u 1 f GHz t 1/w 0 = 25 ps Frequency [GHz] Time [ps] C. Schuster, TUHH 47

48 Effect of Distributed Discontinuities Z 0 Z,,l Z 0 1 inch, 45 Ohm mismatched transmission line at c 0 /2 c f GHz 4l Frequency Response (Scattering Parameters) C. Schuster, TUHH 48

49 300fF 300fF 300fF 300fF Overall Effect of Discontinuities Port1 Port2 2nH Z=49 P=1cm Z=48 P=15cm 2nH Z=52 P=5cm Z=48 P=1cm 2nH C. Schuster, TUHH 49

50 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 50

51 Packaging of Digital Systems Interconnect (Link) Connector C. Schuster, TUHH 51

52 Effect of Coupling Consider two transmission lines in close proximity: (1) Input Aggressor Line (Active Line) (2) Output (3) Near End Victim Line (Quiet Line) (4) Far End C. Schuster, TUHH 52

53 Effect of Coupling Consider two transmission lines in close proximity: I C I C-NE I C-FE Capacitive Crosstalk C. Schuster, TUHH 53

54 Effect of Coupling Consider two transmission lines in close proximity: U L U L-NE U L-FE Inductive Crosstalk C. Schuster, TUHH 54

55 Effect of Coupling Consider two transmission lines in close proximity: (1) Input (2) Output I C (3) Near End (4) Far End U L NEXT = Near End Crosstalk (sum of ind. and cap. crosstalk) FEXT = Far End Crosstalk (difference of ind. and cap. crosstalk) C. Schuster, TUHH 55

56 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce Coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 56

57 Contributors to Line Losses Attenuation usually increases with frequency. The exact calculation can be difficult but for weakly lossy lines: R wl and G wc a convenient approximations exists: a R 2 C L G 2 L C a c a d with a c = attenuation due to conductor losses and a d = attenuation due to dielectric losses. The following dependencies are often found: R ~ w /k G ~ wctand with k = electrical conductivity and tan d = loss tangent. C. Schuster, TUHH 57

58 Time Domain Effect of Losses When taking into account DC losses the effect in the time domain is twofold: edge degradation DC drop Voltage step response without losses step response with losses Time C. Schuster, TUHH 58

59 Frequency Dependence of Losses For the frequency dependence follows with these assumptions: H e l e al e a l c e a l d ~ e const c f e const d f ln H ~ const c f const d f In other words, a typical semilogarithmic plot of the magnitude of the transfer function will be dominated by a square root behavior at lower and a linear behavior at higher frequencies. square root linear total C. Schuster, TUHH 59

60 Dielectric Packaging Materials Dielectric materials are typically classified with respect to their relatice dielectric constant r and their loss tangent tan d: "FR-4" tan d Teflon (PTFE) Silicon Quartz (SiO 2 ) Alumina (Al 2 O 3 ) r C. Schuster, TUHH 60

61 Improving Signal Integrity 1. Match terminations 2. Minimize discontinuities 3. Reduce coupling 4. Limit attenuation 5. Balance deficiencies C. Schuster, TUHH 61

62 Overview of Equalization Techniques Data.. Interconnect Equalizer + Slicer.. Data.. Equalizer Serializer CDR Deserializer Tx Clock Clock & Data Recovery Rx Most high speed serial links nowadays use some EQUALIZATION, i.e. some kind of signal processing technique to correct for the degradations in the interconnect, and thereby improve the quality of signals. When the corrections are applied at the transmitter equalization is sometimes also called DE- EMPHASIS or PRE-EMPHASIS. Apart from continuous time equalization (CTE) signal processing takes place in the discrete time domain / digital filters. C. Schuster, TUHH 62

63 Overview of Equalization Techniques Interconnect Equalization Equalized Response TF = f f f In frequency domain the effect of equalization can be to some extent be visualized as the flattening of the transfer function of the interconnect. An interconncet with a completely flat transfer function would transmit a signal undisturbed apart from a potential amplitude scaling. C. Schuster, TUHH 63

64 Overview of Equalization Techniques Two big classes of (digital, discrete) equalization exist: Equalization Linear Feedforward Equalization (LFE/FFE) - Uses only information from the current and previously received bits - Can be interpreted as a nonrecursive digital filter (finite impulse response filter) Distributed Feedback Equalization (DFE) - Uses a feedback loop after the signal has been decoded by an LFE/FFE - The output of the LFE/FFE is added to the feedback loop resulting in the equalized signal C. Schuster, TUHH 64

65 (5) Improving PI C. Schuster, TUHH 65

66 Improving Power Integrity 1. Decrease PDN impedance 2. Add decoupling 3. Add more decoupling 4. Use several power supplies 5. Use on-chip VRMs C. Schuster, TUHH 66

67 PDN Elements High Power DC Supply Discrete Decoupling Capacitors (various sizes) IC incl. Power/Ground Grid & Integrated Decaps Package incl. Power/Ground Planes Voltage Regulator Module Printed Circuit Board incl. Power/Ground Planes C. Schuster, TUHH 67

68 Improving Power Integrity 1. Decrease PDN impedance 2. Add decoupling 3. Add more decoupling 4. Use several power supplies 5. Use on-chip VRMs C. Schuster, TUHH 68

69 PDN Impedance A typical maximum ripple for ditigal systems is: Du u max 0 maximum ripple 5% to10% With a 10% value the following numbers can be obtained for applications of the early 1990'ies: of 2000 and on: u 0 Z i / i P u 0 avg avg avg Target 5.0 1A W V Ω 0.5Ω u 0 Z i / i P u 0 avg avg avg Target 1.2 V 120A 0.01 Ω 144 W 0.001Ω = 1 m! C. Schuster, TUHH 69

70 Improving Power Integrity 1. Decrease PDN impedance 2. Add decoupling 3. Add more decoupling 4. Use several power supplies 5. Use on-chip VRMs C. Schuster, TUHH 70

71 Low Frequency Equivalent PDN Circuit R L U 0 ~ Z IC ( f ) C. Schuster, TUHH 71

72 Low Frequency Equivalent PDN Circuit including a "decoupling" or "bypass" capacitor: R L U 0 ~ Z IC ( f ) C some nf to some mf C. Schuster, TUHH C. Schuster, TUHH 72

73 Heuristic explanation: Decoupling Effect R L U 0 ~ Z IC ( f ) C Frequency domain: Beyond the resonance frequency the capacitor decouples the part of the PDN that lies "left" of him, i.e. the IC sees only the impedance of the capacitor. Time domain: The capacitor stores charges close to the IC that can become currents needed for fast switching. It is like a "small battery". C. Schuster, TUHH 73

74 Real Word Decoupling Capacitors Unfortunately, there is no ideal capacitor available in the real world! Ideal world: and real world: C R L C R is also is called the EQUIVALENT SERIES RESISTANCE (ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL). As a consequence any real world capacitor behaves approximately like an inductor beyond its resonance frequency: w 0 1/ LC C. Schuster, TUHH 74

75 Improving Power Integrity 1. Decrease PDN impedance 2. Add decoupling 3. Add more decoupling 4. Use several power supplies 5. Use on-chip VRMs C. Schuster, TUHH 75

76 More Decoupling ~ board-level package-level chip-level Amount of charge, size of decoupling capacitance Speed of charge delivery, effective frequency C. Schuster, TUHH 76

77 PDN Impedance More Decoupling ~ board-level package-level chip-level Inductance of VRM Capacitance of Bulk Decaps ESL of Decaps, Pads and Vias Capacitance of P/G Planes & Small Decaps ESL of Planes and Inductance of Package Capacitance of Decaps on Package and IC Remaining On.Chip Inductance Target Impedance 1 MHz 500 MHz 1 GHz 10 GHz C. Schuster, TUHH 77

78 C. Schuster, TUHH 78 0,1,2,...), ( r r 0 n m b n a m c f mn Resonance frequencies of power/ground plane pairs: Examples of standing wave patterns on a rectangular power/ground plane pair. Power/Ground Plane Resoances

79 (6) Wrapping Up C. Schuster, TUHH 79

80 Comprehenisve EMC of Digital Systems The basic goals of SI, PI, and EMI control for a digital system are complementary to each other. SIGNAL INTEGRITY: insure acceptable quality of signals within SNR Target System Frequency POWER INTEGRITY: insure acceptable quality of power delivery within PDN Impedance Target Frequency System EMI: insure acceptable level of interference with the outside EMI Target System Frequency C. Schuster, TUHH 80

Signal Integrity Design of TSV-Based 3D IC

Signal Integrity Design of TSV-Based 3D IC Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues

More information

Design Considerations for Highly Integrated 3D SiP for Mobile Applications

Design Considerations for Highly Integrated 3D SiP for Mobile Applications Design Considerations for Highly Integrated 3D SiP for Mobile Applications FDIP, CA October 26, 2008 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr Contents I. Market and future direction

More information

How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model

How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model HSD Strategic Intent Provide the industry s premier HSD EDA software. Integration of premier

More information

VLSI is scaling faster than number of interface pins

VLSI is scaling faster than number of interface pins High Speed Digital Signals Why Study High Speed Digital Signals Speeds of processors and signaling Doubled with last few years Already at 1-3 GHz microprocessors Early stages of terahertz Higher speeds

More information

Fundamentals of Signal and Power Integrity. Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg

Fundamentals of Signal and Power Integrity. Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg Fundamentals of Signal and Power Integrity Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg Workshop W 23: Signal Integrity of Digital and Analog Systems,

More information

Design of the Power Delivery System for Next Generation Gigahertz Packages

Design of the Power Delivery System for Next Generation Gigahertz Packages Design of the Power Delivery System for Next Generation Gigahertz Packages Madhavan Swaminathan Professor School of Electrical and Computer Engg. Packaging Research Center madhavan.swaminathan@ece.gatech.edu

More information

EMI. Chris Herrick. Applications Engineer

EMI. Chris Herrick. Applications Engineer Fundamentals of EMI Chris Herrick Ansoft Applications Engineer Three Basic Elements of EMC Conduction Coupling process EMI source Emission Space & Field Conductive Capacitive Inductive Radiative Low, Middle

More information

Engineering the Power Delivery Network

Engineering the Power Delivery Network C HAPTER 1 Engineering the Power Delivery Network 1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? The power delivery network consists of all the interconnects in the power supply path

More information

Microcircuit Electrical Issues

Microcircuit Electrical Issues Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the

More information

IEEE CX4 Quantitative Analysis of Return-Loss

IEEE CX4 Quantitative Analysis of Return-Loss IEEE CX4 Quantitative Analysis of Return-Loss Aaron Buchwald & Howard Baumer Mar 003 Return Loss Issues for IEEE 0G-Base-CX4 Realizable Is the spec realizable with standard packages and I/O structures

More information

Advanced Topics in EMC Design. Issue 1: The ground plane to split or not to split?

Advanced Topics in EMC Design. Issue 1: The ground plane to split or not to split? NEEDS 2006 workshop Advanced Topics in EMC Design Tim Williams Elmac Services C o n s u l t a n c y a n d t r a i n i n g i n e l e c t r o m a g n e t i c c o m p a t i b i l i t y e-mail timw@elmac.co.uk

More information

High-Speed Interconnect Technology for Servers

High-Speed Interconnect Technology for Servers High-Speed Interconnect Technology for Servers Hiroyuki Adachi Jun Yamada Yasushi Mizutani We are developing high-speed interconnect technology for servers to meet customers needs for transmitting huge

More information

Lecture 4 RF Amplifier Design. Johan Wernehag, EIT. Johan Wernehag Electrical and Information Technology

Lecture 4 RF Amplifier Design. Johan Wernehag, EIT. Johan Wernehag Electrical and Information Technology Lecture 4 RF Amplifier Design Johan Wernehag, EIT Johan Wernehag Electrical and Information Technology Lecture 4 Design of Matching Networks Various Purposes of Matching Voltage-, Current- and Power Matching

More information

Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material

Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material April 28, 2010 Yu Xuequan, Yanhang, Zhang Gezi, Wang Haisan Huawei Technologies CO., LTD. Shanghai, China Tony_yu@huawei.com

More information

ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY

ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY Rémy FERNANDES Lead Application Engineer ANSYS 1 2018 ANSYS, Inc. February 2, 2018 ANSYS ANSYS - Engineering simulation software leader Our industry reach

More information

Plane Crazy, Part 2 BEYOND DESIGN. by Barry Olney

Plane Crazy, Part 2 BEYOND DESIGN. by Barry Olney by Barry Olney column BEYOND DESIGN Plane Crazy, Part 2 In my recent four-part series on stackup planning, I described the best configurations for various stackup requirements. But I did not have the opportunity

More information

Decoupling capacitor uses and selection

Decoupling capacitor uses and selection Decoupling capacitor uses and selection Proper Decoupling Poor Decoupling Introduction Covered in this topic: 3 different uses of decoupling capacitors Why we need decoupling capacitors Power supply rail

More information

Relationship Between Signal Integrity and EMC

Relationship Between Signal Integrity and EMC Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?

More information

Intel 82566/82562V Layout Checklist (version 1.0)

Intel 82566/82562V Layout Checklist (version 1.0) Intel 82566/82562V Layout Checklist (version 1.0) Project Name Fab Revision Date Designer Intel Contact SECTION CHECK ITEMS REMARKS DONE General Ethernet Controller Obtain the most recent product documentation

More information

Considerations in High-Speed High Performance Die-Package-Board Co-Design. Jenny Jiang Altera Packaging Department October 2014

Considerations in High-Speed High Performance Die-Package-Board Co-Design. Jenny Jiang Altera Packaging Department October 2014 Considerations in High-Speed High Performance Die-Package-Board Co-Design Jenny Jiang Altera Packaging Department October 2014 Why Co-Design? Complex Multi-Layer BGA Package Horizontal and vertical design

More information

ECE 497 JS Lecture - 22 Timing & Signaling

ECE 497 JS Lecture - 22 Timing & Signaling ECE 497 JS Lecture - 22 Timing & Signaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements - Signaling Techniques (4/27) - Signaling

More information

High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi

High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi High Speed Design Issues and Jitter Estimation Techniques Jai Narayan Tripathi (jainarayan.tripathi@st.com) Outline Part 1 High-speed Design Issues Signal Integrity Power Integrity Jitter Power Delivery

More information

Intro. to PDN Planning PCB Stackup Technology Series

Intro. to PDN Planning PCB Stackup Technology Series Introduction to Power Distribution Network (PDN) Planning Bill Hargin In-Circuit Design b.hargin@icd.com.au 425-301-4425 Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane

More information

EMI Reduction on an Automotive Microcontroller

EMI Reduction on an Automotive Microcontroller EMI Reduction on an Automotive Microcontroller Design Automation Conference, July 26 th -31 st, 2009 Patrice JOUBERT DORIOL 1, Yamarita VILLAVICENCIO 2, Cristiano FORZAN 1, Mario ROTIGNI 1, Giovanni GRAZIOSI

More information

Decoupling capacitor placement

Decoupling capacitor placement Decoupling capacitor placement Covered in this topic: Introduction Which locations need decoupling caps? IC decoupling Capacitor lumped model How to maximize the effectiveness of a decoupling cap Parallel

More information

Texas Instruments DisplayPort Design Guide

Texas Instruments DisplayPort Design Guide Texas Instruments DisplayPort Design Guide April 2009 1 High Speed Interface Applications Introduction This application note presents design guidelines, helping users of Texas Instruments DisplayPort devices

More information

Learning the Curve BEYOND DESIGN. by Barry Olney

Learning the Curve BEYOND DESIGN. by Barry Olney by Barry Olney coulmn BEYOND DESIGN Learning the Curve Currently, power integrity is just entering the mainstream market phase of the technology adoption life cycle. The early market is dominated by innovators

More information

To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits

To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits 1 ECEN 720 High-Speed Links: Circuits and Systems Lab6 Link Modeling with ADS Objective To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed

More information

Aries QFP microstrip socket

Aries QFP microstrip socket Aries QFP microstrip socket Measurement and Model Results prepared by Gert Hohenwarter 2/18/05 1 Table of Contents Table of Contents... 2 OBJECTIVE... 3 METHODOLOGY... 3 Test procedures... 4 Setup... 4

More information

The Inductance Loop Power Distribution in the Semiconductor Test Interface. Jason Mroczkowski Multitest

The Inductance Loop Power Distribution in the Semiconductor Test Interface. Jason Mroczkowski Multitest The Inductance Loop Power Distribution in the Semiconductor Test Interface Jason Mroczkowski Multitest j.mroczkowski@multitest.com Silicon Valley Test Conference 2010 1 Agenda Introduction to Power Delivery

More information

100 Gb/s: The High Speed Connectivity Race is On

100 Gb/s: The High Speed Connectivity Race is On 100 Gb/s: The High Speed Connectivity Race is On Cathy Liu SerDes Architect, LSI Corporation Harold Gomard SerDes Product Manager, LSI Corporation October 6, 2010 Agenda 100 Gb/s Ethernet evolution SoC

More information

Aries Kapton CSP socket

Aries Kapton CSP socket Aries Kapton CSP socket Measurement and Model Results prepared by Gert Hohenwarter 5/19/04 1 Table of Contents Table of Contents... 2 OBJECTIVE... 3 METHODOLOGY... 3 Test procedures... 4 Setup... 4 MEASUREMENTS...

More information

Signal Integrity Tips and Techniques Using TDR, VNA and Modeling. Russ Kramer O.J. Danzy

Signal Integrity Tips and Techniques Using TDR, VNA and Modeling. Russ Kramer O.J. Danzy Signal Integrity Tips and Techniques Using TDR, VNA and Modeling Russ Kramer O.J. Danzy Simulation What is the Signal Integrity Challenge? Tx Rx Channel Asfiakhan Dreamstime.com - 3d People Communication

More information

5Gbps Serial Link Transmitter with Pre-emphasis

5Gbps Serial Link Transmitter with Pre-emphasis Gbps Serial Link Transmitter with Pre-emphasis Chih-Hsien Lin, Chung-Hong Wang and Shyh-Jye Jou Department of Electrical Engineering,National Central University,Chung-Li, Taiwan R.O.C. Abstract- High-speed

More information

Minh Quach. Signal Integrity Consideration and Analysis 4/30/2004. Frequency & Time Domain Measurements/Analysis

Minh Quach. Signal Integrity Consideration and Analysis 4/30/2004. Frequency & Time Domain Measurements/Analysis Minh Quach. Signal Integrity Consideration and Analysis 4/30/2004 Frequency & Time Domain Measurements/Analysis Outline Three Measurement Methodologies Direct TDR (Time Domain Reflectometry) VNA (Vector

More information

Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies

Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies 1 Definitions EMI = Electro Magnetic Interference EMC = Electro Magnetic Compatibility (No EMI) Three Components

More information

Quick guide to Power. V1.2.1 July 29 th 2013

Quick guide to Power. V1.2.1 July 29 th 2013 Quick guide to Power Distribution ib ti Network Design V1.2.1 July 29 th 2013 High level High current, high transient Power Distribution Networks (PDN) need to be able to respond to changes and transients

More information

ECE 546 Introduction

ECE 546 Introduction ECE 546 Introduction Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Future System Needs and Functions Auto Digital

More information

The Facts about the Input Impedance of Power and Ground Planes

The Facts about the Input Impedance of Power and Ground Planes The Facts about the Input Impedance of Power and Ground Planes The following diagram shows the power and ground plane structure of which the input impedance is computed. Figure 1. Configuration of the

More information

The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects

The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects Dennis Poulin Anritsu Company Slide 1 Outline PSU Signal Integrity Symposium

More information

High-speed Serial Interface

High-speed Serial Interface High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications

More information

A Novel Embedded Common-mode Filter for above GHz differential signals based on Metamaterial concept. Tzong-Lin Wu

A Novel Embedded Common-mode Filter for above GHz differential signals based on Metamaterial concept. Tzong-Lin Wu c //3 A Novel Embedded Common-mode Filter for above GHz differential signals based on Metamaterial concept Tzong-Lin Wu Professor Graduate Institute of Communication Engineering, National Taiwan University,

More information

Power Distribution Status and Challenges

Power Distribution Status and Challenges Greetings from Georgia Institute of Institute Technology of Technology Power Distribution Status and Challenges Presented by Madhavan Swaminathan Packaging Research Center School of Electrical and Computer

More information

Keysight Technologies Signal Integrity Tips and Techniques Using TDR, VNA and Modeling

Keysight Technologies Signal Integrity Tips and Techniques Using TDR, VNA and Modeling Keysight Technologies Signal Integrity Tips and Techniques Using, VNA and Modeling Article Reprint This article first appeared in the March 216 edition of Microwave Journal. Reprinted with kind permission

More information

Power integrity is more than decoupling capacitors The Power Integrity Ecosystem. Keysight HSD Seminar Mastering SI & PI Design

Power integrity is more than decoupling capacitors The Power Integrity Ecosystem. Keysight HSD Seminar Mastering SI & PI Design Power integrity is more than decoupling capacitors The Power Integrity Ecosystem Keysight HSD Seminar Mastering SI & PI Design Signal Integrity Power Integrity SI and PI Eco-System Keysight Technologies

More information

A VIEW OF ELECTROMAGNETIC LIFE ABOVE 100 MHz

A VIEW OF ELECTROMAGNETIC LIFE ABOVE 100 MHz A VIEW OF ELECTROMAGNETIC LIFE ABOVE 100 MHz An Experimentalist's Intuitive Approach Lothar O. (Bud) Hoeft, PhD Consultant, Electromagnetic Effects 5012 San Pedro Ct., NE Albuquerque, NM 87109-2515 (505)

More information

BASIS OF ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUIT Chapter VI - MODELLING PCB INTERCONNECTS Corrections of exercises

BASIS OF ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUIT Chapter VI - MODELLING PCB INTERCONNECTS Corrections of exercises BASIS OF ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUIT Chapter VI - MODELLING PCB INTERCONNECTS Corrections of exercises I. EXERCISE NO 1 - Spot the PCB design errors Spot the six design errors in

More information

EMI/EMC of Entire Automotive Vehicles and Critical PCB s. Makoto Suzuki Ansoft Corporation

EMI/EMC of Entire Automotive Vehicles and Critical PCB s. Makoto Suzuki Ansoft Corporation EMI/EMC of Entire Automotive Vehicles and Critical PCB s Makoto Suzuki Ansoft Corporation WT10_SI EMI/EMC of Entire Automotive Vehicles and Critical PCB s Akira Ohta, Toru Watanabe, Benson Wei Makoto Suzuki

More information

Electromagnetic Analysis of AC Coupling Capacitor Mounting Structures

Electromagnetic Analysis of AC Coupling Capacitor Mounting Structures Simbeor Application Note #2008_02, April 2008 2008 Simberian Inc. Electromagnetic Analysis of AC Coupling Capacitor Mounting Structures Simberian, Inc. www.simberian.com Simbeor : Easy-to-Use, Efficient

More information

EM Noise Mitigation in Electronic Circuit Boards and Enclosures

EM Noise Mitigation in Electronic Circuit Boards and Enclosures EM Noise Mitigation in Electronic Circuit Boards and Enclosures Omar M. Ramahi, Lin Li, Xin Wu, Vijaya Chebolu, Vinay Subramanian, Telesphor Kamgaing, Tom Antonsen, Ed Ott, and Steve Anlage A. James Clark

More information

Taking the Mystery out of Signal Integrity

Taking the Mystery out of Signal Integrity Slide - 1 Jan 2002 Taking the Mystery out of Signal Integrity Dr. Eric Bogatin, CTO, GigaTest Labs Signal Integrity Engineering and Training 134 S. Wolfe Rd Sunnyvale, CA 94086 408-524-2700 www.gigatest.com

More information

AltiumLive 2017: Component selection for EMC

AltiumLive 2017: Component selection for EMC AltiumLive 2017: Component selection for EMC Martin O Hara Victory Lighting Ltd Munich, 24-25 October 2017 Component Selection Passives resistors, capacitors and inductors Discrete diodes, bipolar transistors,

More information

DesignCon Design of Gb/s Interconnect for High-bandwidth FPGAs. Sherri Azgomi, Altera Corporation

DesignCon Design of Gb/s Interconnect for High-bandwidth FPGAs. Sherri Azgomi, Altera Corporation DesignCon 2004 Design of 3.125 Gb/s Interconnect for High-bandwidth FPGAs Sherri Azgomi, Altera Corporation sazgomi@altera.com Lawrence Williams, Ph.D., Ansoft Corporation williams@ansoft.com CF-031505-1.0

More information

TABLE OF CONTENTS 1 Fundamentals Transmission Line Parameters... 29

TABLE OF CONTENTS 1 Fundamentals Transmission Line Parameters... 29 TABLE OF CONTENTS 1 Fundamentals... 1 1.1 Impedance of Linear, Time-Invariant, Lumped-Element Circuits... 1 1.2 Power Ratios... 2 1.3 Rules of Scaling... 5 1.3.1 Scaling of Physical Size... 6 1.3.1.1 Scaling

More information

PDN design and analysis methodology in SI&PI codesign

PDN design and analysis methodology in SI&PI codesign PDN design and analysis methodology in SI&PI codesign www.huawei.com Asian IBIS Summit, November 9, 2010, Shenzhen China Luo Zipeng (luozipeng@huawei.com) Liu Shuyao (liushuyao@huawei.com) HUAWEI TECHNOLOGIES

More information

RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications. Revision Date: March 18, 2005

RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications. Revision Date: March 18, 2005 RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction

More information

Lecture 4. Maximum Transfer of Power. The Purpose of Matching. Lecture 4 RF Amplifier Design. Johan Wernehag Electrical and Information Technology

Lecture 4. Maximum Transfer of Power. The Purpose of Matching. Lecture 4 RF Amplifier Design. Johan Wernehag Electrical and Information Technology Johan Wernehag, EIT Lecture 4 RF Amplifier Design Johan Wernehag Electrical and Information Technology Design of Matching Networks Various Purposes of Matching Voltage-, Current- and Power Matching Design

More information

Design for EMI & ESD compliance DESIGN FOR EMI & ESD COMPLIANCE

Design for EMI & ESD compliance DESIGN FOR EMI & ESD COMPLIANCE DESIGN FOR EMI & ESD COMPLIANCE All of we know the causes & impacts of EMI & ESD on our boards & also on our final product. In this article, we will discuss some useful design procedures that can be followed

More information

Flip-Chip for MM-Wave and Broadband Packaging

Flip-Chip for MM-Wave and Broadband Packaging 1 Flip-Chip for MM-Wave and Broadband Packaging Wolfgang Heinrich Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH) Berlin / Germany with contributions by F. J. Schmückle Motivation Growing markets

More information

Custom Interconnects Fuzz Button with Hardhat Test Socket/Interposer 1.00 mm pitch

Custom Interconnects Fuzz Button with Hardhat Test Socket/Interposer 1.00 mm pitch Custom Interconnects Fuzz Button with Hardhat Test Socket/Interposer 1.00 mm pitch Measurement and Model Results prepared by Gert Hohenwarter 12/14/2015 1 Table of Contents TABLE OF CONTENTS...2 OBJECTIVE...

More information

Predicting and Controlling Common Mode Noise from High Speed Differential Signals

Predicting and Controlling Common Mode Noise from High Speed Differential Signals Predicting and Controlling Common Mode Noise from High Speed Differential Signals Bruce Archambeault, Ph.D. IEEE Fellow, inarte Certified Master EMC Design Engineer, Missouri University of Science & Technology

More information

QPairs QTE-DP/QSE-DP Final Inch Designs in Serial ATA Generation 1 Applications 5mm Stack Height. REVISION DATE: January 12, 2005

QPairs QTE-DP/QSE-DP Final Inch Designs in Serial ATA Generation 1 Applications 5mm Stack Height. REVISION DATE: January 12, 2005 Application Note QPairs QTE-DP/QSE-DP Final Inch Designs in Serial ATA Generation 1 Applications 5mm Stack Height REVISION DATE: January 12, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed

More information

EMC cases study. Antonio Ciccomancini Scogna, CST of America CST COMPUTER SIMULATION TECHNOLOGY

EMC cases study. Antonio Ciccomancini Scogna, CST of America CST COMPUTER SIMULATION TECHNOLOGY EMC cases study Antonio Ciccomancini Scogna, CST of America antonio.ciccomancini@cst.com Introduction Legal Compliance with EMC Standards without compliance products can not be released to the market Failure

More information

10 Safety earthing/grounding does not help EMC at RF

10 Safety earthing/grounding does not help EMC at RF 1of 6 series Webinar #3 of 3, August 28, 2013 Grounding, Immunity, Overviews of Emissions and Immunity, and Crosstalk Contents of Webinar #3 Topics 1 through 9 were covered by the previous two webinars

More information

Advanced Transmission Lines. Transmission Line 1

Advanced Transmission Lines. Transmission Line 1 Advanced Transmission Lines Transmission Line 1 Transmission Line 2 1. Transmission Line Theory :series resistance per unit length in. :series inductance per unit length in. :shunt conductance per unit

More information

DesignCon Effect of Power Plane Inductance on Power Delivery Networks. Shirin Farrahi, Cadence Design Systems

DesignCon Effect of Power Plane Inductance on Power Delivery Networks. Shirin Farrahi, Cadence Design Systems DesignCon 2019 Effect of Power Plane Inductance on Power Delivery Networks Shirin Farrahi, Cadence Design Systems shirinf@cadence.com, 978-262-6008 Ethan Koether, Oracle Corp ethan.koether@oracle.com Mehdi

More information

Wideband On-die Power Supply Decoupling in High Performance DRAM

Wideband On-die Power Supply Decoupling in High Performance DRAM Wideband On-die Power Supply Decoupling in High Performance DRAM Timothy M. Hollis, Senior Member of the Technical Staff Abstract: An on-die decoupling scheme, enabled by memory array cell technology,

More information

EE290C Spring Lecture 2: High-Speed Link Overview and Environment. Elad Alon Dept. of EECS

EE290C Spring Lecture 2: High-Speed Link Overview and Environment. Elad Alon Dept. of EECS EE290C Spring 2011 Lecture 2: High-Speed Link Overview and Environment Elad Alon Dept. of EECS Most Basic Link Keep in mind that your goal is to receive the same bits that were sent EE290C Lecture 2 2

More information

Signal Integrity, Part 1 of 3

Signal Integrity, Part 1 of 3 by Barry Olney feature column BEYOND DESIGN Signal Integrity, Part 1 of 3 As system performance increases, the PCB designer s challenges become more complex. The impact of lower core voltages, high frequencies

More information

Class-D Audio Power Amplifiers: PCB Layout For Audio Quality, EMC & Thermal Success (Home Entertainment Devices)

Class-D Audio Power Amplifiers: PCB Layout For Audio Quality, EMC & Thermal Success (Home Entertainment Devices) Class-D Audio Power Amplifiers: PCB Layout For Audio Quality, EMC & Thermal Success (Home Entertainment Devices) Stephen Crump http://e2e.ti.com Audio Power Amplifier Applications Audio and Imaging Products

More information

Demystifying Vias in High-Speed PCB Design

Demystifying Vias in High-Speed PCB Design Demystifying Vias in High-Speed PCB Design Keysight HSD Seminar Mastering SI & PI Design db(s21) E H What is Via? Vertical Interconnect Access (VIA) An electrical connection between layers to pass a signal

More information

High-Speed Circuits and Systems Laboratory B.M.Yu. High-Speed Circuits and Systems Lab.

High-Speed Circuits and Systems Laboratory B.M.Yu. High-Speed Circuits and Systems Lab. High-Speed Circuits and Systems Laboratory B.M.Yu 1 Content 1. Introduction 2. Pre-emphasis 1. Amplitude pre-emphasis 2. Phase pre-emphasis 3. Circuit implantation 4. Result 5. Conclusion 2 Introduction

More information

Q2 QMS-DP/QFS-DP Series 11 mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications. Revision Date: February 22, 2005

Q2 QMS-DP/QFS-DP Series 11 mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications. Revision Date: February 22, 2005 Q2 QMS-DP/QFS-DP Series 11 mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications Revision Date: February 22, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in

More information

CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL

CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL POWER INTEGRITY ANALYSIS AND MANAGEMENT I CIRCUITS Raj Nair Donald Bennett PRENTICE HALL Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown

More information

CPS-1848 PCB Design Application Note

CPS-1848 PCB Design Application Note Titl CPS-1848 PCB Design Application Note June 22, 2010 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (408) 284-8200 Fax: (408) 284-3572 2010 About this Document This document is

More information

Effect of Power Noise on Multi-Gigabit Serial Links

Effect of Power Noise on Multi-Gigabit Serial Links Effect of Power Noise on Multi-Gigabit Serial Links Ken Willis (kwillis@sigrity.com) Kumar Keshavan (ckumar@sigrity.com) Jack Lin (jackwclin@sigrity.com) Tariq Abou-Jeyab (tariqa@sigrity.com) Sigrity Inc.,

More information

Comparison of IC Conducted Emission Measurement Methods

Comparison of IC Conducted Emission Measurement Methods IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 3, JUNE 2003 839 Comparison of IC Conducted Emission Measurement Methods Franco Fiori, Member, IEEE, and Francesco Musolino, Member, IEEE

More information

DP Array DPAM/DPAF Final Inch Designs in Serial ATA Generation 1 Applications 10mm Stack Height. REVISION DATE: January 11, 2005

DP Array DPAM/DPAF Final Inch Designs in Serial ATA Generation 1 Applications 10mm Stack Height. REVISION DATE: January 11, 2005 Application Note DP Array DPAM/DPAF Final Inch Designs in Serial ATA Generation 1 Applications 10mm Stack Height REVISION DATE: January 11, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed

More information

A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems

A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems M. Meghelli 1, A. Rylyakov 1, S. J. Zier 2, M. Sorna 2, D. Friedman 1 1 IBM T. J. Watson Research Center 2 IBM

More information

Chip-to-module far-end TX eye measurement proposal

Chip-to-module far-end TX eye measurement proposal Chip-to-module far-end TX eye measurement proposal Raj Hegde & Adam Healey IEEE P802.3bs 400 Gb/s Ethernet Task Force March 2017 Vancouver, BC, Canada 1 Background In smith_3bs_01a_0915, it was shown that

More information

MICTOR. High-Speed Stacking Connector

MICTOR. High-Speed Stacking Connector MICTOR High-Speed Stacking Connector Electrical Performance Report for the 0.260" (6.6-mm) Stack Height Connector.......... Connector With Typical Footprint................... Connector in a System Report

More information

CMT2300AW Schematic and PCB Layout Design Guideline

CMT2300AW Schematic and PCB Layout Design Guideline AN141 CMT2300AW Schematic and PCB Layout Design Guideline Introduction This document is the CMT2300AW Application Development Guideline. It will explain how to design and use the CMT2300AW schematic and

More information

EMC problems from Common Mode Noise on High Speed Differential Signals

EMC problems from Common Mode Noise on High Speed Differential Signals EMC problems from Common Mode Noise on High Speed Differential Signals Bruce Archambeault, PhD Alma Jaze, Sam Connor, Jay Diepenbrock IBM barch@us.ibm.com 1 Differential Signals Commonly used for high

More information

DL-150 The Ten Habits of Highly Successful Designers. or Design for Speed: A Designer s Survival Guide to Signal Integrity

DL-150 The Ten Habits of Highly Successful Designers. or Design for Speed: A Designer s Survival Guide to Signal Integrity Slide -1 Ten Habits of Highly Successful Board Designers or Design for Speed: A Designer s Survival Guide to Signal Integrity with Dr. Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises, www.bethesignal.com

More information

Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems. A Design Methodology

Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems. A Design Methodology Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems A Design Methodology The Challenges of High Speed Digital Clock Design In high speed applications, the faster the signal moves through

More information

Automotive PCB SI and PI analysis

Automotive PCB SI and PI analysis Automotive PCB SI and PI analysis SI PI Analysis Signal Integrity S-Parameter Timing analysis Eye diagram Power Integrity Loop / Partial inductance DC IR-Drop AC PDN Impedance Power Aware SI Signal Integrity

More information

Signal Integrity Modeling and Measurement of TSV in 3D IC

Signal Integrity Modeling and Measurement of TSV in 3D IC Signal Integrity Modeling and Measurement of TSV in 3D IC Joungho Kim KAIST joungho@ee.kaist.ac.kr 1 Contents 1) Introduction 2) 2.5D/3D Architectures with TSV and Interposer 3) Signal integrity, Channel

More information

Physical RF Circuit Techniques and Their Implications on Future Power Module and Power Electronic Design

Physical RF Circuit Techniques and Their Implications on Future Power Module and Power Electronic Design Physical RF Circuit Techniques and Their Implications on Future Power Module and Power Electronic Design Adam Morgan 5-5-2015 NE IMAPS Symposium 2015 Overall Motivation Wide Bandgap (WBG) semiconductor

More information

if the conductance is set to zero, the equation can be written as following t 2 (4)

if the conductance is set to zero, the equation can be written as following t 2 (4) 1 ECEN 720 High-Speed Links: Circuits and Systems Lab1 - Transmission Lines Objective To learn about transmission lines and time-domain reflectometer (TDR). Introduction Wires are used to transmit clocks

More information

Plastic straw: future of high-speed signaling

Plastic straw: future of high-speed signaling Supplementary Information for Plastic straw: future of high-speed signaling Ha Il Song, Huxian Jin, and Hyeon-Min Bae * Korea Advanced Institute of Science and Technology (KAIST), Department of Electrical

More information

LVDS Flow Through Evaluation Boards. LVDS47/48EVK Revision 1.0

LVDS Flow Through Evaluation Boards. LVDS47/48EVK Revision 1.0 LVDS Flow Through Evaluation Boards LVDS47/48EVK Revision 1.0 January 2000 6.0.0 LVDS Flow Through Evaluation Boards 6.1.0 The Flow Through LVDS Evaluation Board The Flow Through LVDS Evaluation Board

More information

EM Analysis of RFIC Transmission Lines

EM Analysis of RFIC Transmission Lines EM Analysis of RFIC Transmission Lines Purpose of this document: In this document, we will discuss the analysis of single ended and differential on-chip transmission lines, the interpretation of results

More information

06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07

06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07 06-496r3 SAS-2 Electrical Specification Proposal Kevin Witt SAS-2 Phy Working Group 1/16/07 Overview Motivation Multiple SAS-2 Test Chips Have Been Built and Tested, SAS-2 Product Designs have Started

More information

DL-150 The Ten Habits of Highly Successful Designers. or Design for Speed: A Designer s Survival Guide to Signal Integrity

DL-150 The Ten Habits of Highly Successful Designers. or Design for Speed: A Designer s Survival Guide to Signal Integrity Slide -1 Ten Habits of Highly Successful Board Designers or Design for Speed: A Designer s Survival Guide to Signal Integrity with Dr. Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises, www.bethesignal.com

More information

Phil Lehwalder ECE526 Summer 2011 Dr. Chiang

Phil Lehwalder ECE526 Summer 2011 Dr. Chiang Phil Lehwalder ECE526 Summer 2011 Dr. Chiang PLL (Phase Lock Loop) Dynamic system that produces a clock in response to the frequency and phase of an input clock by varying frequency of an internal oscillator.

More information

1. TABLE OF FIGURES APPLICATION NOTE OVERVIEW EMI...5

1. TABLE OF FIGURES APPLICATION NOTE OVERVIEW EMI...5 APPLICATION NOTE 8.7 Rev 1.0 General Guidelines for Reduced Electromagnetic Interference utilizing the SMSC LAN83C175 EPIC 10/100 Mbps Ethernet Controller and Physical Layer Devices By Thomas Greene and

More information

PHY Layout APPLICATION REPORT: SLLA020. Ron Raybarman Burke S. Henehan 1394 Applications Group

PHY Layout APPLICATION REPORT: SLLA020. Ron Raybarman Burke S. Henehan 1394 Applications Group PHY Layout APPLICATION REPORT: SLLA020 Ron Raybarman Burke S. Henehan 1394 Applications Group Mixed Signal and Logic Products Bus Solutions November 1997 IMPORTANT NOTICE Texas Instruments (TI) reserves

More information

A Technical Discussion of TDR Techniques, S-parameters, RF Sockets, and Probing Techniques for High Speed Serial Data Designs

A Technical Discussion of TDR Techniques, S-parameters, RF Sockets, and Probing Techniques for High Speed Serial Data Designs A Technical Discussion of TDR Techniques, S-parameters, RF Sockets, and Probing Techniques for High Speed Serial Data Designs Presenter: Brian Shumaker DVT Solutions, LLC, 650-793-7083 b.shumaker@comcast.net

More information

The Ground Myth IEEE. Bruce Archambeault, Ph.D. IBM Distinguished Engineer, IEEE Fellow 18 November 2008

The Ground Myth IEEE. Bruce Archambeault, Ph.D. IBM Distinguished Engineer, IEEE Fellow 18 November 2008 The Ground Myth Bruce Archambeault, Ph.D. IBM Distinguished Engineer, IEEE Fellow barch@us.ibm.com 18 November 2008 IEEE Introduction Electromagnetics can be scary Universities LOVE messy math EM is not

More information

Objectives of transmission lines

Objectives of transmission lines Introduction to Transmission Lines Applications Telephone Cable TV (CATV, or Community Antenna Television) Broadband network High frequency (RF) circuits, e.g., circuit board, RF circuits, etc. Microwave

More information