1. TABLE OF FIGURES APPLICATION NOTE OVERVIEW EMI...5

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1 APPLICATION NOTE 8.7 Rev 1.0 General Guidelines for Reduced Electromagnetic Interference utilizing the SMSC LAN83C175 EPIC 10/100 Mbps Ethernet Controller and Physical Layer Devices By Thomas Greene and Paul Brant 1. TABLE OF FIGURES APPLICATION NOTE OVERVIEW EMI AN EMI OVERVIEW...5 Radiated Emissions & Radiated Immunity...6 Conducted Emissions & Conducted Immunity EMI MODELS...7 Radiated Emissions Differential Mode Common Mode...7 Conducted Immunity Differential Mode Common Mode...9 EMI occurrences Frequency Amplitude Time Impedance Dimension CAUSES OF EMI AND THEIR SOLUTIONS...10 Power Supply Droop...11 Decoupling for Line Impedance Circuits logic gate switching Connectors Digital Circuit Ground Noise Ground Bounce Sources of Noise Ground Bounce Prevention GENERAL GUIDELINES AND CONSIDERATIONS...18 Crossovers...18 Short Traces...18 Impedance Match Traces...18 Create a Moat...18 Surface Microstrip...19 Differential Surface Microstrip...19 Differential Surface Microstrip Over a Void...21 Stripline...22 Differential Stripline...23 Propagation Delay...23 Copper Layer Considerations...24

2 Permittivity Considerations...24 Recommended Circuit Board Layups...24 Crosstalk in Slotted Ground Planes...25 Differential-mode Radiation...26 Common-Mode Radiation...26 Decoupling Capacitors...28 Bypass Capacitors...30 Bulk Capacitors...30 Bulk Decoupling Capacitor...30 Line Charging Capacitance ETHERNET SPECIFIC GUIDELINES...32 TP TRANSMIT INTERFACE for the LAN83C TP RECEIVE INTERFACE for the LAN 83C TP TRANSMIT OUTPUT CURRENT SET LAN83C CABLE SELECTION...37 TRANSMITTER DROOP...37 FX INTERFACE General Connection to 3.3V Transceivers...37 Connection to 5V Transceivers...39 Disabling the FX Interface ETHERNET SPECIFIC GUIDELINE SUMMARY DESIGN EXAMPLE - ETHERNET + MODEM PC CARD...43 SMSC LAN83C175 Cardbus Dual Function Reference Schematics...45 SMSC LAN83C175 Cardbus Dual Function Reference Layout Power Layer Ground Layer Layer 4 ing ing Bottom Side ing Top Side...57 Ground Plane Implementation...58 A.1.1. Transmission Line Effects...59 A.1.2. Series Termination Resistor...62 A.1.3. Parallel Termination Resistor...63 A.1.4. Thevenin Network...63 A.1.5. RC Network (AC Parallel)...63 A.1.6. Diode Network...63 A.1.7. Decoupling Capacitors...64 A.1.8. Bypass Capacitors...66 A.1.9. Bulk Capacitors...66 A Impedance...67 A Impedance Control...67 A Unused Inputs...68 A Crosstalk...68 A Loop Area...70 A Component Layout...83 A Decoupling Capacitor Placement...83 A Bulk Capacitor Placement...83 A Trace Length...84 A Isolation...84 A Routing of High Speed Traces...85 A Proper Trace Layout...85 A Bob Smith Termination...86 A Standard Configuration Termination...87 A Preferred Wiring Arrangement - NIC or Hub...88 A Plane Management...89 A RJ45 Shielding

3 A Managing the PCB Traces PROPAGATION DELAY CALCULATIONS...91 For Stripline Calculations:...91 For Surface Microstrip Calculations: REFERENCES DISCLAIMER Arkay Drive Hauppauge, NY (631) FAX (631)

4 1. Table of Figures Figure 1. Differential Mode Radiation from PCB...7 Figure 2. Common-Mode Radiation from System Cables...8 Figure 3. Simple Circuit...8 Figure 4. Differential Mode Interference...9 Figure 5. Common Mode Interference...9 Figure 6. Noise Model of Integrated Circuit...11 Figure 7. Decoupling Capacitor Added to Noise Model...12 Figure 8. Clock Oscillator Circuit with Ferrite Bead...12 Figure 9. Decoupling for Line Impedance Circuits...13 Figure 10. Equation for Correct Bypass Capacitor...14 Figure 11. Circuit Model Showing Ground Bounce...16 Figure 12. Surface Microstrip...19 Figure 13. Differential Surface Microstrip...20 Figure 14 - Differential Surface Microstrip Over a Void...21 Figure 15 - Stripline construction, sandwiched between two reference (Ground/VCC) planes...22 Figure 16 - Four layer circuit board construction...25 Figure 17 - Six layer board construction...25 Figure 18 - Six layer board construction...25 Figure 19 - Typical Network Interface Card Schematic...33 Figure 20 - Typical Switching Port Schematic...34 Figure 21 - Typical External PHY Schematic...35 Figure 22 - Connection to 3.3 Volt Fiber OpticTransceivers...39 Figure 23 - Connection to 5 Volt Fiber Optic Transceivers...40 Figure 24 SMSC LAN83C175 10/100 Ethernet Plus V.90 Modem Multi Function Cardbus Design...44 Figure 25 - LAN83C175 Ethernet plus Modem Power layer...53 Figure 26 - LAN83C175 Ethernet plus Modem Ground Layer...54 Figure 27 - Bottom Side ing...55 Figure 28 - Bottom Side ing Layer...56 Figure 29 - TopSide ing Layer...57 Figure 30 - Transmission Line Effects...60 Figure 31 - Common Termination Types...62 Figure 32 - Crosstalk with Relation to Distance...68 Figure 33. Spectral Bandwidth...71 Figure 34. Quiet I/O Ground Plane...73 Figure 35 - EMI Results in Ground Dispersal...74 Figure 36. Reducing Fan Out...75 Figure 37. Moating Examples...79 Figure 38. Typical Recommended PCB Stackups...81 Figure 39. Logic Placement with Respect to Speed...82 Figure 40. Correct Routing Techniques...84 Figure 41. Bob Smith Common Mode Termination Configuration...86 Figure 42. Standard Termination Configuration...88 Figure 43. Straight-Through Wiring with Internal Crossover in Hub

5 2. APPLICATION NOTE OVERVIEW This document examines EMC (Electromagnetic Compatibility) issues relating to SMSC s design and development of a production ready Multifunction PC CARD. The PC Card includes a 10/100 Ethernet Adapter and V.90 Modem. The focus of this application note is to go over the details required to design with EMC (Electromagnetic Compatibility) in mind. This type of design methodology will allow the system designer to develop a card with low EMI emissions allowing the device to pass the most stringent emissions certifications. A specific application example will be offered to illustrate specific design criteria which hardware designers would need to consider in implementing a marketable and certifiable design. This example will be in the form of a real multi-function PC Card adapter device that is primarily used in portable PC devices also known as notebook computers. 3. EMI The control and minimization of EMC is a technology that is, out of necessity, growing rapidly. Manufacturers and regulatory agencies have made efforts to control this problem but the issue of meeting these ever tightening specifications is left to the system designer. EMC can no longer be a fix, designed in at the last moment, but must be a directed effort between the circuit designer, layout engineer, software engineer and purchaser. This paper examines what can be done to reduce the risk of having a product fail EMC approval. The example shown in this paper will examine these issues. The growth of concern over electromagnetic compatibility (EMC) in electronic systems continues to rise in the years since the USA Federal Communications Commission (FCC), who is responsible for regulating communication equipment, proclaimed that there shall be no more pollution of the electromagnetic spectrum. Still, designers have not yet fully come to grips with a major source and victim of electromagnetic interference--- the PCB. The most critical stage for addressing EMI is during the circuit board design. Numerous experiences can be recounted about eleventh hour attempts at solving EMI problems by retrofit because EMC was given no attention during design. This retrofit of a PC Card or other design ultimately costs much more than if addressed during the design stage. EMC problems hold up production and generally make managers unhappy. With these facts in mind, let's address electromagnetic compatibility considerations in PCB design. A fundamental EMC design principle requires that EMI be attenuated at its source on the PC board. This strategy confines noise to small regions of a given PC board and reduces the possibility that high frequency noise will couple to other circuits (often called receptor or victim circuits) that may radiate the noise more efficiently through interconnecting wires or openings in a product s shielding. Attacking EMI at the source generally provides the most cost effective design approach, since filtering is targeted only to a few specific noise generating circuits, rather than to every single possible noise receptor in the entire product. Effective source filtering also helps limit overall EMC design costs by reducing the need for additional shielding that would otherwise be necessary to confine unfiltered high frequency noise components. 4. An EMI Overview Three elements must be present for an EMI event to exist. These three elements are noise source, propagation path, and susceptor. Noise source on a PCB relates to frequency-generating circuits, component radiation within a plastic package, ground bounce, electrically-long trace lengths, poor impedance control, cable interconnects, and the like. Propagation path refers to the medium that carries the RF energy; such as free space or metallic interconnects. A Susceptor is the device which receives undesired RF interference. If one of these three elements is removed, an EMI event cannot exist. It is our task to determine which of the three is the easiest to 5

6 eliminate. We have no control over the susceptor, as we generally do not know what the susceptor will be. Suppression affects noise source, and is the easiest of the three to implement. EMI produced by electrical equipment is classified according to its dominant mode of propagation, either as radiated emissions of energy through space (similar to television and radio signal transmission) or conducted emissions of energy along wires (similar to telephone signals and AC power transmission). When dealing with emissions, a general rule of thumb applies. The higher the frequency, the greater the likelihood of a radiated coupling path; the lower the frequency, the greater the likelihood of a conducted coupling path. Radiated Emissions & Radiated Immunity A major source of radiated emissions from modern electronic equipment is digital circuitry mounted on printed-circuit boards. Digital signals have rapid transitions which cause significant energy in the signal harmonics. The spectrum of digital signals often extends to relatively high frequencies where the radiating structures are generally more efficient. There are two types of basic radiating structures in digital electronics: the magnetic loop and the electric dipole. Radiation near a loop is predominantly magnetic. This type of radiation is called differential mode. Radiation near an electric dipole is predominantly electric. This type of radiation is called common mode. Radiators found in electronic equipment can be approximated by one of these two types. Emissions being produced by a circuit can wind up affecting a system in one of two ways or both. The emissions can simply be produced by the circuit and exit the system. The emissions may also couple with other circuits in the system, affect those circuits adversely and/or exit the system through the second circuit. Emissions that simply exit the system through the air are thought of in terms of Radiated Emissions. Radiated Immunity is a circuit s characteristics when subjected to radiated emissions. When speaking in terms of Radiated Immunity, the source of the radiated emission can be intra-system or extrasystem. Conducted Emissions & Conducted Immunity Any signal inside a piece of electronic equipment can potentially appear as a conducted emission. There are two varieties of conducted emissions that concern us. The first variety is differential-mode. That is a signal that appears between the input terminals of a circuit. The other variety of conducted emissions is called common-mode. A common-mode signal appears between each input terminal and a third point, the common-mode reference. That reference may be the equipment chassis, an earth ground, or some other point. The signal noise created by each of these instances can wind up effecting a system in the following manner. The signal noise can be produced by the circuit and exit the system through I/O cables or power supply cables. This instance is referred to as Conducted Emissions. This is characterized as intra-system signals exiting the system. Extra-system noise coupled to circuits via either differential-mode or common-mode can adversely effect operation of those circuits. Again, the signal noise enters the system through I/O cables or power supply cables. Conducted immunity describes how circuits subjected to this signal noise respond. 6

7 5. EMI Models Radiated Emissions Differential Mode Differential-mode radiation is the result of current flowing around loops formed by the conductors of the circuit. These loops act as small antennas radiating magnetic fields. Although these signal current loops are necessary for circuit operation, their size and area must be controlled during the design process, in order to limit the radiation. Differential-mode radiation can be modeled as occurring from a small loop antenna. The magnitude of the signal is based upon the area of the loop, the current in the circuit, the frequency of the signal and the distance from the source. Figure 1 illustrates this occurrence on a PCB. Radiated Emission I C Ground Figure 1. Differential Mode Radiation from PCB Common Mode Common-mode radiation is the result of undesired voltage drops in the circuit that cause some parts of the system to be at a common-mode potential above true ground. Often this is the result of voltage drops in the digital logic ground system. Common-mode RF currents are generally observed in I/O interconnects. Rarely is common-mode noise observed internal to the PCB. Figure 2. Common-Mode Radiation from System Cables illustrates this occurrence. 7

8 Ground Plane or Grid I/O Cable VN PCB Ground Wire Ground Conducted Immunity Figure 2. Common-Mode Radiation from System Cables Differential Mode In Figure 3. Simple Circuit we show a simple circuit consisting of a signal source, V S, and a load, R L. In Figure 4. Differential Mode Interference we show what happens when differential mode interference is introduced into the circuit by an outside source. As is shown, an interference voltage, V D, appears between the two input terminals, and an interference current, I D, flows in the circuit. The result is noise at the load. If, for instance, the load is a logic gate in a computer, and the amplitude of V D is sufficiently high, it is possible for the gate to incorrectly change states. +V S R L - V S Figure 3. Simple Circuit 8

9 +V S I D V D R L - V S I D Figure 4. Differential Mode Interference Common Mode Figure 5. Common Mode Interference shows what happens when a ground loop is added to our circuit. Ground loops, which are undesirable current paths through a grounded body (such as a chassis), are usually caused by poor design or by the failure of some component. In the presence of an interference source, common-mode currents, I C, and a common-mode voltage, V C, can develop, with the ground loop acting as the common mode reference. The common-mode current flows on both input lines, and has the same instantaneous polarity and direction (the current and voltage are in phase), and returns through the common-mode reference. The common-mode voltage between each input and the common-mode reference is identical +V S I C R L - V S I C 2 x IC V C 2 x I C Figure 5. Common Mode Interference EMI occurrences When speaking about EMI occurrences, there are five major factors relating the amount radiation that occurs. They are: 9

10 The Frequency of the radiated signals(s). The Amplitude of the radiated signals(s). Dependent time relationships. Impedance matching. Physical / Dimension layout issues Frequency Frequency is the starting point for any EMI analysis. The whole spectrum (typically 30 MHz to 1000 MHz) must be analyzed. Each offending frequency must be identified. Typically, due to harmonics, there will be patterns noticeable across a range of the spectrum. If there are several fundamental frequencies involved in the system, the analysis can be tricky. Once the fundamental is suppressed, however, all the subsequent harmonics also are attenuated (most of the time). Upon identifying offending frequencies it is simply a matter of addressing the corresponding circuits. Hopefully, if the designer has followed the guidelines presented here, there will be no need to go back and re-engineer the offending circuits Amplitude The next step in analyzing an EMI situation is determining the amplitude of the offending frequencies. The following sentence should be clarified a bit, think in terms of a designer with limited English. A designer must be aware of how serious the EMI situation is at a given frequency. A designer needs to be aware of how far out at that frequency the system is. Typically, if the system is way out, this usually indicates some basic, fundamental rule is being broken. If the system is only 2 or 3 db out, there may be some tough going ahead. Usually, for quality reasons, a margin of 2 or 3 db is also imposed on the system. So to be out by 3 db may mean the designer has to quiet the system by 5 or 6 db. This can be difficult. That is why it is imperative to have the design as clean as possible from an EMI standpoint from the beginning Time Time patterns may be noticed. Is the problem continuous (free running clock signal) or does it coincide with an event (disk drive read/write operation)? These may be clues used to identify the problem. Unfortunately, when concerning Ethernet, many problems are radiated out through the Ethernet cables. With Fast Ethernet, there is always activity on the cable, so if there is a problem on the cable, it will always be there. That is another reason why precautions must be taken, especially in the design and layout of the Ethernet front end Impedance The designer must be aware of the impedance of the source, the impedance of the receptor and the impedance of the path between the two Dimension For transmission of RF energy to occur, an antenna is needed. The physical dimensions that exist based on trace length or slots within an enclosure determine which frequencies are observed. In general, the obvious rule is to keep all traces as short as possible and all openings as small as possible. 6. Causes of EMI and Their Solutions The amplitude versus frequency characteristic of the harmonic envelope emphasize a crucial signal spectra concept for EMC engineers: the deliberate slowing (increasing the risetime of) a signal results in large reductions in higher order harmonics. Stated from a different perspective, preserving a given bandwidth of a signal corresponds to maintaining a certain rise and fall time; increasing its rise and fall times reduces its bandwidth and EMI potential; reducing its rise and fall times increases the signal s bandwidth and its potential to cause EMI. 10

11 Power Supply Droop PC boards generate EMI that originates from periodic switching of digital circuits. A simple noise model of a digital integrated circuit (IC) is shown in Figure 6. Each time the IC output switches state, it causes high frequency current to flow from the PC board power distribution bus (Vcc and ground ). This action will introduce a small differential noise voltage drop or sag across the board s power bus. Since this process will repeat with each transition of the IC s output, the noise that is induced on the PC board power and Ground will oscillate at a frequency equal to the operating frequency of the IC. Additional ICs that reside on the PC board will see this noise voltage and couple it to other areas of the system. Power supply and data cables that are connected to the PC board power and ground bus will also transport and radiate the IC switching noise throughout and outside of the system. Differential Noise on PCB Power and Ground + - Power Supply + V (t) - I (t) PCB Power Bus Model Integrated Circuit Current Source Noise Model Figure 6. Noise Model of Integrated Circuit To reduce the magnitude of the board impedance, circuit designers add decoupling capacitors across the power and ground conductors of the PC board in an attempt to provide a local source of charge for each active device. This technique can also be viewed as placing a high frequency short circuit across the active device s power and ground pins, as shown in Figure 7. 11

12 + Z PCB Power Bus Impedance V (t) - Decoupling Capacitor Integrated Circuit Figure 7. Decoupling Capacitor Added to Noise Model While decoupling capacitors may provide adequate noise filtering at frequencies up to 75 MHz, their performance at higher frequencies will be dramatically reduced by the presence of circuit resonances. These resonances s arise from the interaction of the decoupling capacitors with device lead and interconnect inductance. Many EMC engineers have observed and solved frustrating noise problems that arise unexpectedly from unique combinations of noise frequencies, PC board layouts and decoupling capacitors. While the resonant behavior of decoupling capacitor arrangements limits their effectiveness at higher frequencies, the performance of ferrites actually improves with increasing frequencies. Since EMI suppression ferrite s present essentially resistive (lossy) impedance at high frequencies, they cannot by themselves introduce performance limiting circuit resonance s. When used in conjunction with decoupling capacitors, ferrites can provide additional EMI source suppression by blocking and dissipating power bus noise generated by high-speed logic devices. Note that a capacitor still must be used at the power input pin of the active device, since the ferrite by its nature will block the high speed switching current that the device requires to operate. Figure 8. Shows an example of a ferrite bead and capacitor filter that is often used in personal computer clock oscillator circuits. Ferrite Bead VCC 50 Mhz Osc To PCB Power Bus Figure 8. Clock Oscillator Circuit with Ferrite Bead 12

13 Decoupling for Line Impedance Circuits High-speed CMOS Integrated Circuits impose special decoupling and PCB layout requirements. Adhering to these requirements will ensure that maximum advantage is gained in system and EMC performance when using CMOS devices. Local high frequency decoupling is required to supply power to the chip when it is transitioning from a LOW to a HIGH value. This power is necessary to charge the load capacitance or drive a line impedance. For most power distribution networks, the typical impedance can be between 50 Ω and 100 Ω. This impedance appears in series with the load impedance and will cause a droop in the V CC at the part. This droop limits the available voltage swing at the local node, unless some form of decoupling is used. This drooping of rails will cause the rise and fall times to become elongated. Consider the example presented in Figure 9 which is used to illustrate the calculation of the amount of decoupling necessary. This circuit utilizes an octal buffer driving a 100 Ω bus from a point somewhere in the middle. Data Bus Buffer output sees net 50 ohm load 50 ohm load line on Ioh - Voh Characteristic shows low-to-high Step of 4.8 volts 100 ohms V OUT 4.9 V Buffer, 1 of 8 Ground Plane 0.1 V I OH 4 ns 94 ma 100 ohms 0 ma Worst Case Octal Drain = 8 x 94 ma = 750 ma Figure 9. Decoupling for Line Impedance Circuits Being in the middle of the bus, the driver will see two 100 Ω loads in parallel, or an effective impedance of 50 Ω. To switch the line from rail to rail, a drive of 94 ma is needed (4.8V/50 ς) and more than 750 ma will be required if all eight lines switch at once. This instantaneous current requirement will generate a voltage drop across the impedance of the power lines, causing the actual V CC at the chip to droop. This droop limits the voltage swing available to the driver. The net effect of the voltage droop will be to lengthen device rise and fall times and slow system operation. A local de-coupling capacitor is required to act as a low impedance supply for the driver chip during high current demands. It will maintain the voltage within acceptable limits and keep rise and fall times to a minimum. The necessary values for de-coupling capacitors can be calculated with the formula given in Figure

14 V CC Bus C B I=750 ma Bypass Capacitors Specify Vcc Droop = 0.1Volts max during switching time of 4 ns Figure 10. Equation for Correct Bypass Capacitor Decoupling capacitors need to be of the high K ceramic type with low equivalent series resistance (ESR), consisting primarily of series inductance and series resistance. Capacitors using Z5U dielectric have suitable properties and make a good choice for decoupling capacitors; they offer minimum cost and effective performance logic gate switching When the logic gate switches, there is a current transient that occurs on the power supply lead. This current transient flows through the ground and power system. Assuming the ground inductance has already been minimized as much as possible, the major problem now is the voltage drop that occurs across the inductance of the power supply line. The transient current flowing through this inductance produces a large noise voltage that appears at the V cc terminal of the logic gate. The magnitude of the power supply voltage transient can be reduced by decreasing the inductance and/or decreasing the transient current flowing through the inductance. The inductance can be minimized by using a power plane or grid, as in the case of the ground system. The transient current can be minimize or eliminated by supplying the current from another source, such as a capacitor near the logic gate. The noise voltage across the gate is then a function of the decoupling capacitor C d and the wiring between it and the gate. The type of capacitor used and its value and placement with respect to the IC are all important in determining the capacitor s effectiveness. Decoupling capacitors are still required to control the radiated emission from the transient power supply current. The radiated emission is proportional to the loop area enclosed by the transient current Connectors Q = C V charge on capacitor I = C dv/dt C = I dt/dv = 750 ma x 4 ns / 0.1 V = uf Select Cb = uf or greater Board to board connections is often the most troublesome high-speed connections because a continuous signal path is not possible due to mechanical constraints. There are two primary approaches to reduce the signal discontinuity. The first approach assumes that the connector style is fixed, so the pin-out must be modified to provide a good signal path. Non-differential signals are referenced between the active signal line and a reference plane; either a voltage or ground plane, whichever is closest. 14

15 Board to board connections are often troublesome because of mismatches in characteristic impedance. Non-differential signal conductors rely on controlled geometries and nearby AC reference planes (either DC voltage or ground planes) for impedance control. These geometries are interrupted in the connector. Efforts to control signal and reference pin quantity and location in the connector should be made to control electrical performance. To reduce the noise, more reference pins must be added to reduce the distance and sharing problems. Generally a 3:1 signal to reference pin ratio is sufficient. The best ratio is 1:1, but may be too expensive, or consume too much real estate. The second approach is to modify the connector. The intent is to minimize the discontinuity distance between boards. Either shortening the pin length, or adding reference ground plane within the connector can be used. In digital circuits, the internal noise sources are the major concern. Internal noise is the result of the following: (1) ground bus noise, (2) power bus noise, (3) transmission line reflections, and (4) cross-talk. To minimize the noise generated by these internal noise sources, digital logic systems must be designed with: A low inductance ground system. A source of charge near each logic gate Digital Circuit Ground Noise Ground noise is more of a problem than power supply noise. The ground noise is produced by transient power supply currents and signal-return currents. The power supply transients can be controlled by proper use of decoupling capacitors, but the signal currents in the ground cannot be decoupled or bypassed. Transient ground currents are a primary source of both intra-system noise voltages, and conducted and radiated emissions. To minimize the noise from transient ground currents, the impedance of the ground must be minimized Ground Bounce Sources of Noise Ground bounce occurs as a result of the intrinsic characteristics of the leadframes and bond wires of the packages used to house CMOS devices. As edge rates and drive capability increase in advanced logic families, the effects of these intrinsic electrical characteristics become more pronounced. One of these parasitic electrical characteristics is the inductance found in all leadframe materials. Figure 11. Circuit Model Showing Ground Bounce shows a simple circuit model for a CMOS device in a leadframe driving a standard test load. 15

16 V CC I CC L2 Output Voltage V L3 V IN R1 I I = C L x (dv / dt) C L R L L1 I GB = L1 x (di / dt) Figure 11. Circuit Model Showing Ground Bounce The inductor L1 represents the parasitic inductance in the ground lead of the package; inductor L2 represents the parasitic inductance in the power lead of the package. Inductor L3 represents the parasitic inductance in the output lead of the package. The resistor R1 represents the output impedance of the device output, and the capacitor and resistor, C L and R L, represent the standard test load on the output of the device. The three waveforms shown represent how ground bounce is generated. The top waveform shows the voltage (V) across the load as it is switched from a logic HIGH to a logic LOW. The output slew rate is dependent upon the characteristics of the output transistor, and the inductors L1 and L3, and C L, the load capacitance. In order to change the output from a HIGH to a LOW, current must flow to discharge the load capacitance. The second waveform shows the current that is generated as the capacitor discharges [ I = -C L x (dv / dt)]. As it changes, this current causes a voltage to be generated across the inductances in the circuit. The formula for the voltage across an inductor is V = L x (dl / dt). The third waveform shows the voltage that is induced across the inductance in the ground lead due to the changing currents V GB = L1 x (dl / dt)]. This induced voltage creates what is known as ground bounce. Because the inductor is between the external system ground and the internal device ground, the induced voltage causes the internal ground to be at a different potential than the external ground. This shift in potential causes the device inputs and outputs to behave differently than expected because they are referenced to the internal device ground, while the devices which are either driving into the inputs or being driven by the outputs are referenced to the their own device ground. External to the device, ground bounce causes input thresholds to shift and output levels to change. Although this discussion is limited to ground bounce generated during HIGH-to-LOW transitions, it should be noted that the ground bounce is also generated during LOW-to-HIGH transitions. This ground bounce has much smaller amplitude and therefore does not present the same concern. 16

17 There are many factors that affect the amplitude of the ground bounce. Included are: Number of outputs switching simultaneously. More outputs results in more ground bounce. Type of output load: capacitive loads generate two to three times more ground bounce than typical system traces. Increasing the capacitive load to approximately 60 pf - 70 pf, increases ground bounce. Beyond 70 pf, ground bounce drops off due to the filtering effect of the load itself. Moving the load away from the output also reduces the ground bounce. Location of the output pin: outputs closer to the ground pin exhibit less ground bounce than those further away due to effectively lower L1 and L3. Voltage: lowering VCC reduces ground bounce Ground Bounce Prevention Observing either one of the following rules is sufficient to avoid running into any of the problems associated with ground bounce: First, use caution when driving asynchronous TTL-level inputs from CMOS outputs. Ground bounce glitches may cause spurious inputs that will alter the state of nonclocked logic. Second, use caution when running control lines (set, reset, load, clock, chip select) which are glitch-sensitive through the same devices that drive data or address lines. Use board design practices that reduce any additive noise sources, such as cross-talk, reflections, etc. Ground bounce produces several symptoms: Altered device states. Propagation delay degradation. Undershoot on active outputs. The worst-case undershoot will be approximately equal to the worst-case quiet output noise. 17

18 7. General Guidelines and Considerations This section describes what the design and Layout Engineer needs to keep in mind when designing for EMI compliance. The guidelines that will be discussed are applicable for most, if not all, designs for digital and/or mixed signal applications. The items that will be discussed are: Minimize and/or eliminate crossovers. Strive for short trace lengths between devices (eg. PHY, transformers and connectors) Match impedance of traces to each other and to ground When possible, create a moat under transformers Surface Microstrip Technology Differential Surface Microstrip over and not over a Void Stripline and Differential Stripline issues Propagation Delay considerations Copper Layer Considerations Permittivity Considerations Recommended Circuit Board Layups Crosstalk in Slotted Ground Planes Differential-mode Radiation Common-Mode Radiation Decoupling, Bypass and Bulk Capacitors Line Charging Capacitance issues Crossovers Eliminate crossovers if possible When unavoidable use the PCB instead of transformers for consistent crosstalk performance Locate crossovers on the chip side of the transformers. The CMR chokes should help with any additional common mode noise caused by the vias. Short Traces Overall performance is enhanced when PCB trace lengths are reduced Improves return loss performance due to reduced capacitance Emissions should also improve as short traces are less susceptible to radiated system noise and will be less likely to generate noise Impedance Match Traces In general, the match of all traces is desired. However, specific traces need only be addressed as described below. Traces of differential signals(+/-) should be equal length to prevent common mode noise generation Traces should be impedance matched to the impedance of the cable (100Ω) and the PHY (50Ω, 100Ω, etc.) Create a Moat It is recommended that signal traces, V CC and ground (GND) planes not be routed under transformers. Routing under transformers may increase cable noise by radiating into the magnetics and from the magnetics onto the GND plane. This moat creates the separation of chassis GND and the analog/digital V CC /GND planes. 18

19 Surface Microstrip When designing a PCB, special care must be taken to match the output impedance of any driver or buffer device to the PCB trace. Different signal types require different construction techniques. Surface Microstrip involves a single signal trace separated from a reference (Ground/VCC) plane by a dielectric layer. Typically, in the case of Ethernet designs, seventy-five or fifty ohms impedance to ground is involved. Here, we are concerned with line-to-ground impedance. This construction is used in four or six layer boards. An ideal microstrip transmission line consists of a narrow conductor separated from an infinite ground plane by a layer of dielectric material. In the simplest case (an uncoated line), the conductor sits on top of the dielectric, surrounded on the sides and top only by air. (Taken from IPC-D-317A, paragraph 5.5.1) Z o = 87 ln [5.98 H / (.8W + T)] / ( ε r ) C o = 0.67 ( ε r ) / ln [5.98 H / (.8 W + T )] Where: H = Dielectric thickness W = Line width T = Line thickness 0.1< W/H < < ε r < 15 ε r = typ 4.5 W [ohms] [ pf/inch] T Trace Dielectric H Gnd/Pwr Plane Figure 12. Surface Microstrip Note: For Online Calculator: HTTP/ Differential Surface Microstrip Differential Surface Microstrip involves two differential signals. It is also reffered to as Coupled Surface Microstrip. This construction involves two differentially paired signal traces separated from a reference (Ground/VCC) plane by a dielectric layer. Typically, in our case, Ethernet applications involve 100, 78 or 50 ohms impedance. Here we are concerned with line-to-line impedance. 19

20 This construction is used in four or six layer boards. S T W Trace W Trace Dielectric H Gnd/Pwr Plane Figure 13. Differential Surface Microstrip 20

21 Differential Surface Microstrip Over a Void Differential Surface Microstrip Over a Void involves two differential paired signal traces with no reference (Ground/VCC) plane under them. Typically, in our case, Ethernet applications require 100, 78 or 50 ohms impedance. Here we are concerned with line-to-line impedance. This construction is used in four or six layer boards and is shown in Figure 14 - Differential Surface Microstrip Over a Void. S T W Trace W Trace Dielectric H Figure 14 - Differential Surface Microstrip Over a Void 21

22 Stripline Stripline construction involves a single signal trace sandwiched between two reference (Ground/VCC) planes. Typically, in our case, clock application circuits 75 or 50 ohms to ground only. Here we are concerned with line-to-ground impedance. This construction is used in six layer boards only. A stripline is a thin, narrow conductor embedded between two AC ground planes. Since all electric and magnetic field lines are contained between the planes, the stripline configuration has the advantage that EMI will be suppressed except for lines near edges of the printed circuit board. Because of the presence of ground planes on both sides of a stripline circuit, the capacitance of the line is increased and the impedance is decreased from the microstrip case. (Taken from IPC-D-317A, paragraph 5.5.3) Z o = 60 ln [1.9 (2H + T) / (.8W + T)] ε r C o = 1.41 ε r / ln [3.81 H / (.8 W + T )] For W/H < 2 Where: [ohms] [ pf/inch] H = Distance between one line and one reference plane T = Line thickness W = Line width W / (H - T) < 0.35 T / H < 0.25 Gnd/Pwr Plane Dielectric H1 W T Trace Dielectric H2 Gnd/Pwr Plane Figure 15 - Stripline construction, sandwiched between two reference (Ground/VCC) planes For Online Calculator: 22

23 Differential Stripline Differential Stripline involves two differential paired signal traces sandwiched between two reference (Ground/VCC) planes. Typically, in our case, Ethernet applications involve 100 ohms impedance. Here we are concerned with line-to-line impedance. This construction is used in six layer boards only. Propagation Delay Propagation delay is the time required for a signal to travel along a transmission line, or the time required for a logic device to perform its function and present a signal at its output. The propagation delay depends only on the relative permittivity and is not a function of the line width, thickness or spacing. Transmission signal propagation delay may be calculated by: T pd = ε r / C For Stripline calculations: Where: ε r = relative permittivity C = speed of light in a vacuum Typical ε r values = C =.0118 in/ps T pd = 4.5 /.0118 T pd = ps/in T pd =.179 ns/in For Surface Microstrip calculations: Typical ε r values = C =.0118 in/ps T pd = 2.75 /.0118 T pd = ps/in T pd =.140 ns/in The location of the trace in the PCB contributes to the relative permittivity. When the electric field stays in the board, the effective permittivity is bigger and signals propagate more slowly. The electric field surrounding a circuit trace encapsulated between two ground planes stays completely inside the board, yielding an effective dielectric constant, for typical FR-4 printed circuit board material, of 4.5. Traces laid on the outside surface of the printed circuit board (outer traces) share their electric field between the air on one side and the FR-4 material on the other, yielding an effective dielectric about halfway between 1.0 and 4.5. Outer layer PCB traces are always faster than inner traces. (Taken from High Speed Digital Design, paragraph 1.2) 23

24 Copper Layer Considerations Typically, 1/2 oz., 1 oz. & 2 oz. copper sheets are used. Copper Layer (oz per ft 2 ) Thickness 1/2 ounce copper 0.7 mils thick ( ) 1 ounce copper 1.4 mils thick ( ) 2 ounce copper 2.8 mils thick ( ) Permittivity Considerations The dielectric layers have two relative permittivity values associated with them. Depending upon what type of construction of PCB, the permittivity of the dielectric layers differs. The first permittivity value is that of the material itself with relation to air. The Relative Permittivity, ε r, of a substance is defined as the ratio of the permittivity of the material to that of free space. The term relative permittivity is preffered to dielectric constant, since this quantity is not constant, but varies with several parameters. Factors that influence the relative permittivity of a given material include: the electrical frequency at which the measurement is performed, temperature, and extent of water absorption. In addition, if the material is a composite e.g. a reinforced laminate, the value of ε r may vary enormously as the relative amount of each component of the composite is changed. (Taken from IPC-D-317A, paragraph 5.2.1) The second permittivity value is that which influences a trace in and on a PCB. The Effective Relative Permittivity, ε' r, is the relative permittivity that is experienced by an electrical signal transmitted along a conductive path. An experimental value of ε' r may be obtained using a time domain reflectometry (TDR) technique. However, it is frequently more convenient to calculate a value of ε' r from known values of ε r. (Taken from IPC-D-317A, paragraph 5.2.2) Recommended Circuit Board Layups Figure 16, Figure 17 and Figure 18 present typical multi-layer printed circuit board layer constructions. These figures provide examples useful in microstrip, stripline and dual stripline transmission line configurations. For optimum EMI performance, the highest frequency signals should be placed on internal layers between reference planes. Power distribution planes should be close to each other to provide maximum distributed capacitance for decoupling high speed signals. The methodology in terms of the number of layers that are required for a particular design is a function of board size, device layout and cost. Obviously, the increased number of layers increases the board cost. 24

25 Power Ground Figure 16 - Four layer circuit board construction Power Ground Figure 17 - Six layer board construction Power Ground Crosstalk in Slotted Ground Planes Figure 18 - Six layer board construction Ground slots happen when a layout engineer runs out of room on the regular routing layers and needs to cram a signal trace on the ground plane layer. This is done by cutting a long slot in the ground plane layer and laying the trace in the slot. Ground slots add inductance to traces passing perpendicularly over the slot and increase crosstalk. It is strongly recommended that ground slots should not be used. (Taken from High Speed Digital Design, paragraph 5.3) 25

26 Differential-mode Radiation Differential-mode radiation shown in Equation 1 - Differential-mode radiation can be modeled as occurring from a small loop antenna. For a small loop of area (A), carrying current (I), the magnitude of the electric field (E) measured in free space at a distance (r), in the far field, the equation (Weeks 1964, p. 565, eq. 91) is equal to: Equation 1 - Differential-mode radiation E = x (f 2 A I) (1/r) sinυ E is described in volts/meter, f is in Hertz, A) is in square meters, I is in amperes and r is described in meters. The above equation is for a small loop located in space, with no reflecting surfaces nearby. Most measurements of radiation from electronic products, however, are made in an open field over a ground plane. The extra ground reflection can add as much as 6 db to the emission measurement. To account for this, the above equation must be multiplied by a factor of 2. Correcting for the ground reflection and assuming an orientation that maximizes emission, the equation can be re-written as: Equation 2 - Differential-mode radiation Correcting for the ground reflection E = 263 x ( f 2 A I ) (1/r) The above equation shows that the radiation is proportional to the current (I), the loop area (A), and the square of the frequency (f). Therefore, radiation can be controlled by (1) reducing the magnitude of the current, (2) reducing the frequency or harmonic content of the current, and/or (3) reducing the loop area. In the design of a digital system, the recommended method to control differential-mode radiation is to minimize the area enclosed by current flow. This means placing signal leads and their associated ground-return leads close together. This is especially important for clock leads, backplane wiring, and interconnecting cables. For example, if 25 ma of current at a frequency of 30 MHz is flowing around a 10-cm 2 loop, the electric field strength measured at a distance of 3 m will be 197 µv/m. This is almost twice the allowable emission for an FCC class B product (intended for residential applications) in the United States. The maximum loop area that will not exceed a specified emission level can be determined by solving the above equation for the loop area (A). Thus the Equation 3 - Maximum loop area is : Equation 3 - Maximum loop area A = 380 E r / f 2 I where E is the radiation limit in microvolts per meter, r is the distance between the loop and measuring antenna in meters, f is the frequency in megahertz, I is the current in milliamperes, and A is the loop area in square centimeters. For example, for 25 ma of current at 30 MHz, the maximum loop area that will limit the radiation to 100 µv/m at a distance of 3 m (the FCC Class B limit) is 5 cm 2. Common-Mode Radiation Differential-mode radiation is easily controlled in the design and layout of a product. On the other hand, common-mode radiation is harder to control and normally determines the overall emission performance of the product. Common-mode radiation emanates from the cables in the system. The radiated frequencies are determined by the common-mode potential (usually the ground voltage), The frequencies radiated are not the same as differential-mode signals in the cable. 26

27 Common-mode emission can be modeled as a short (less than one-quarter wavelength) monopole antenna (the cable) driven by a voltage (the ground voltage). For a short monopole antenna of length (L) over a ground plane, the magnitude of the electric field strength (E), measured at a distance (r) in the far field the equation can be written shown in Equation 4 - Common-mode emission (Weeks 1964, p. 310, Eq. 39b) is: Equation 4 - Common-mode emission E = (4π x 10-7 (f I L) sinυ) / r where (E) is in volts/meter, (f) is in hertz, (I) is the common-mode current on the cable (antenna) in amperes, and (L) and (r) are in meters. The above equation is valid for an ideal antenna with a uniform current distribution. For a real antenna, the current goes to zero at the open end of the wire. In practice, a uniform current distribution can be achieved if the antenna is capacitively loaded with a metal plate at the open end. This is called a capacitor plate or top-hat loaded antenna. This configuration is approximated when the antenna (cable) connects to another piece of equipment that is either grounded or, if it is not grounded, has sufficient capacitance to ground. The capacitor plate antenna then closely approximates the ideal uniform current antenna model. Assuming an orientation that maximizes the emission ( Υ = 908 ), the above equation can be re-written as shown in Equation 5 Radiation Relationships: Equation 5 Radiation Relationships E = 12.6 x 10-7 ( f I L ) ( 1 / r ) The above equation shows that the radiation is proportional to the frequency, the length of the antenna and the magnitude of the common-mode current on the antenna. The primary method of minimizing this radiation is to limit the common-mode current. 27

28 Decoupling Capacitors Decoupling capacitors must supply high-frequency ( MHz) currents; therefore they should be low inductance, high-frequency capacitors. For this reason disk ceramic or multilayer ceramic capacitors are preferred. Decoupling capacitors need to be of the high K ceramic type with low equivalent series resistance (ESR), consisting primarily of series inductance and series resistance. Capacitors using Z5U dielectric have suitable properties and make a good choice for decoupling capacitors; they offer minimum cost and effective performance Components that switch logic states must be RF decoupled. This is because the switching energy generated by logic components will be injected into the power distribution system. This switching energy will be transferred to other logic circuits or subsections as common-mode and/or differential mode RF noise. Typically, one selects a capacitor with a self resonant frequency in the range of MHz for circuits with edge rates of 2 nano seconds or less. Typical multilayer PCBs are self resonant in the MHz range. Proper selection of decoupling capacitors, along with knowing the self-resonant frequency of the PCB assembly (acting as one large bulk capacitor) will provide enhanced EMI suppression of digital switching noise. Surface mount devices have a higher self resonant frequency by up to two orders of magnitude. This higher self resonant frequency is due to less lead length inductance. Aluminum electrolytic capacitors are ineffective for high frequency decoupling and are best suited for power supply subsystems or power line filtering. In addition to bypass capacitors, high-frequency RF decoupling capacitors must always be provided in all clock generation areas. To do this, calculate the decoupling capacitance value needed to suppress RF switching noise for all significant clock harmonics. Choose a capacitor with a self-resonant frequency higher than the clock harmonics requiring suppression, generally considered to be the fifth harmonic of the original clock frequency. In addition to this selection criteria, one must be cognizant of the amount of energy the capacitor provides to the component for proper operation. Decoupling capacitors ideally should be able to supply all the DC current necessary during a state transition. Calculation of the local point-source charge of the decoupling capacitor is represented by the following equation shown in Equation 6 - local point-source charge of the decoupling capacitor: Equation 6 - local point-source charge of the decoupling capacitor C = V t C = 20 ma 100 mv 5 ns = uf or 1000 pf where: C = capacitance I = current transient V = allowable power supply ripple (change) t = switching time 28

29 This equation does not calculate self-resonant frequency, only the localized source charge required to remove RF switching noise from the power distribution system. As observed, use of 0.1µF capacitors in today s products are usually insufficient for optimal decoupling when the edge rate of the device is faster than 5 nano seconds. Use of decoupling capacitors on two layer boards is, required to reduce power supply ripple. Decoupling capacitors for low frequency applications are usually not needed when multilayer boards are used, given that the capacitance between the power plane and ground planes provides overall decoupling for low frequency or slower edge rate components and are more efficient than discrete components. A benefit of using multi-layer PCBs is that placement of the power and ground planes adjacent to each other which creates on large decoupling capacitor, generally in the range of MHz. This internal decoupling capacitor usually provides adequate decoupling for slow speed (slow edge rate) designs. If components have signal edges (t r ) slower than 10 ns (e.g., standard TTL logic), use of low, self-resonant frequency decoupling capacitors is generally not required as the majority of decoupling is performed by the internal power and ground planes. Decoupling capacitors provide current to devices during switching transients until the power supply can respond. High frequency switching, which is composed of a broad spectrum of current frequencies, requires several low to high frequency capacitors. This is because a single capacitor typically cannot provide such a broad frequency. Most designers tend to use decoupling capacitors that are too large for the application. All capacitors have some inductance in series with their capacitance. The inductance is the result of the capacitor structure, the capacitor leads, and the external paths used to connect the capacitor to the IC terminals. Because of this combination of capacitance and inductance, the capacitor will, at some frequency, become self-resonant. At the self-resonant frequency the capacitor is a very low-impedance and an effective bypass. Above the self-resonant frequency the circuit becomes inductive, its impedance increases with frequency, and consequently it performs poorly as a decoupling capacitor. The resonant frequency of a series L-C circuit is shown in Equation 7 - resonant frequency of a series L-C circuit on page 29: Equation 7 - resonant frequency of a series L-C circuit f = 1 2 L C Consider the case of a µf decoupling capacitor with an internal inductance of 1 nh. If the inductance of the wiring that connects it to the IC can be kept to 30 ηh, the circuit will be self-resonant at 29 MHz. For the same amount of inductance, the larger the capacitor value, the lower the self-resonant frequency will be. Therefore a decoupling capacitor larger than necessary should not be used because it will have a lower self-resonant frequency. On the other hand, if the capacitor is too small in value, it will not have sufficient charge storage to supply the transient current needed by the IC without an excessive drop in voltage. Therefore an optimum-value capacitor exists for every application. Many experiments have been performed on 14 and 16 pin ICs to find the optimum value for this capacitor. Often the minimum noise voltage occurred with a 470 to 1000 pf capacitor. The best type (or value) of decoupling capacitor for a specific application can be found by measuring the noise voltage across the IC with the various types (or values) of capacitor being considered. The smallest value capacitor that will do the job is the best choice. Seldom should a decoupling capacitor be larger than 0.01 µf, except in the case of some random-access memory (RAM) ICs which have large, instantaneous current demands during the refresh cycle. 29

30 In the case of dynamic RAM (DRAM) ICs, however, all the cells are refreshed at the same time, and there are more cells in a RAM than there are gates in a logic IC. Current must be supplied to all these cells at the same time during the refresh cycle; therefore larger value decoupling capacitors are required for dynamic RAMS than logic ICs. Typically a 256-K DRAM requires a 0.1 µf decoupling capacitor. Bypass Capacitors Bypass capacitors are commonly used to divert common-mode RF currents that are present on cable shields by creating an AC short to chassis ground. RF currents are, in reality, an AC component (sine wave). Bypass capacitors must be placed where I/O interconnects attach to the PCB. If the braid of the cable is floating, or not bonded to chassis ground, a bypass capacitor is required to remove commonmode currents present on the cable shield from either radiating into free space or causing a disruption to the chassis due to an immunity event. Bulk Capacitors Bulk capacitors maintain proper DC voltage and current to components when these devices switch all data, address and control signals simultaneously under maximum capacitive load. Large power consuming components will cause voltage fluctuations on the power distribution system. These fluctuations will cause improper circuit performance due to voltage sags, ground bounce and ground noise voltage. Bulk capacitors also provide large amounts of energy storage to maintain voltage and current requirements of switching components. Bulk capacitors play no significant role in EMI control. Bulk capacitors, usually tantalum dielectric, must be used in addition to higher self-resonant frequency decoupling capacitors to provide DC power for components and to prevent power plane RF modulation. Low frequency capacitance is often termed bulk capacitance. This capacitance is used to recharge power planes and higher frequency charging capacitors, and provide switching current for lower frequency requirements. Bulk Decoupling Capacitor The IC decoupling capacitors must be recharged. The recharging currents occur at a considerably lower frequency than in the case of the individual IC decoupling capacitors and are supplied by a bulk decoupling capacitor located on the printed wiring board. The value of the bulk capacitor is not critical, but it should be greater than ten times the sum of all the values of the decoupling capacitors. The bulk decoupling capacitor should be located where power comes onto the board. If more than 20 ICs are on the board, more than one bulk capacitor should be used and located around the board so that there is a capacitor close to every 15 to 20 ICs. The bulk decoupling capacitor should have a small equivalent series inductance. Tantalum electrolytic or metalized polycarbonate capacitors are appropriate for this application because they both have low internal inductance. Aluminum electrolytic capacitors have inductances an order of magnitude higher and should not be used. 30

31 Line Charging Capacitance Line charging capacitance provides switching current to charge the signal line after the signal reaches the lines. The charge current is required until the line reaches its quiescent state. If insufficient capacitance/current is provided, the edge transition time will degrade. Two types of line charging capacitance are required: one for capacitive lines and one for transmission lines. Capacitive line charging requires a relatively slower charging rate than a transmission line, but must provide more current. A transmission line requires a slower, but typically longer pulse to keep the line charged until all of the reflections are over. When adjacent power planes are provided high speed switching current is provided prior to current being supplied by the discrete decoupling capacitors. This capacitance is increased as the planes are spaced closer together. 31

32 8. Ethernet Specific Guidelines This section will focus on specific Ethernet Board Design details to reduce EMI. The following sections will discuss the Twisted Pair Transmit and Receive interface from and to the MAC, PHY and magnetics. The PHY device has its own unique characteristics such as: Voltage or current driven TX output impedance Output capacitance Common mode noise (low or high frequency) Rise and fall times As a result, issues such as Twisted Pair output current settings will be discussed as well as the proper cable selection. Transmitter Droop aspects will be referenced as well as discussing Optical Fiber Interfaces. Note: Fiber optics does not cause any EMI. However for completeness, it is discussed. However, some circuitry related to the fiber electronics might couple onto other circuits. The coding and signal conversion necessary to interface to Ethernet cabling is performed by a Physical Layer (PHY) device. The PHY is a mixed signal device and is therefore very sensitive to various sources of noise. A typical example schematic of the LAN83C183 used in an adapter card application is shown in Figure 19 - Typical Network Interface Card Schematic, a hub application is shown in Figure 20 - Typical Switching Port Schematic, and an external PHY application is shown in Figure 21 - Typical External PHY Schematic. TP TRANSMIT INTERFACE for the LAN83C183 The interface between the Twisted Pair (here on referred to as TP) outputs on TPO± and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in Figure 19 through Figure 21. The transformer for the transmitter is recommended to have a winding ratio of 1:1 with a center tap on the primary winding tied to V DD, as shown Figure 19 through Figure 21. The specifications for such a transformer are shown in Table 1. Sources for the transformer are listed in Table 2. The transmit output needs to be terminated with two external termination resistors in order to meet the output impedance and return loss requirements of IEEE It Is recommended that these two external resistors be connected from V DD to each of the TPO± outputs, and their value should be chosen to provide the correct termination impedance when looking back through the transformer from the twisted pair cable, as shown in Figure 19 - Typical Network Interface Card Schematic through Figure 21 - Typical External PHY Schematic. The value of these two external termination resistors depends on the type of cable driven by the device. Refer to the Cable Selection Section for more details on choosing the value of these resistors. To minimize common mode output noise and to aid in meeting radiated emissions requirements, it may be necessary to add a common mode choke on the transmit outputs as well as add common mode bundle termination. The qualified transformers mentioned in Table 2 - TP Transformer Sources all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown in Figure 19 through Figure 21. Common mode bundle termination maybe needed and can be achieved by tying the unused pairs in the RJ45 to chassis ground through 75 Ω resistors and a 0.01 µf capacitor, as shown in Figure 19 through Figure 21. To minimize noise pickup into the transmit path in a system or on a PCB, the loading on TPO± should be minimized and both outputs should always be loaded equally. 32

33 TP RECEIVE INTERFACE for the LAN 83C183 Receive data is typically transformer coupled into the receive inputs on TPI± and terminated with external resistors as shown in Figure 19 through Figure 21. The transformer for the receiver is recommended to have a winding ration of 1:1, as shown in Figure 19 through Figure 21. The specifications for such a transformer are shown in Table 1 - TP Transformer Specification. Sources for the transformer are listed in Table 2 - TP Transformer Sources. Figure 19 - Typical Network Interface Card Schematic 33

34 Figure 20 - Typical Switching Port Schematic 34

35 Figure 21 - Typical External PHY Schematic The receive input needs to be terminated with the correct termination impedance to meet the input impedance and return loss requirements of IEEE In addition, the receive TP inputs need to be attenuated. It is recommended that both the termination and attenuation be accomplished by placing four external resistors in series across the TPI± inputs as shown in Figure 19 through Figure 21. The resistors should be 25%/25%/25%/25% of the total series resistance, and the total series resistance should be equal to the Characteristic Impedance of the cable (100 Ω for UTP, 15O Ω for STP). It is also recommended that a 0.01 µf capacitor be placed between the center of the series resistor string and V DD in order to provide an AC ground for attenuating common mode signal at the input. This capacitor is also shown Figure 19 through Figure 21. To minimize common mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common mode choke on the receive input as well as add common mode bundle termination. The qualified transformers mentioned in Table 2 all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown Figure 19 through Figure 21. Common mode bundle termination may be needed and can be achieved by tying the receive secondary centertap 35

36 and the unused pairs in the RJ45 to chassis ground through 75 Ω resistors and a 0.01 µf capacitor, as shown in Figure 19 through Figure 21. In order to minimize noise pickup into the receive path in a system or on a PCB, loading on TPI± should be minimized and both inputs should be loaded equally. Table 1 - TP Transformer Specification Parameter Specification Transmit Receive Turns Ratio 1:1 CT 1:1 Inductance, (µh Min) Leakage Inductance, (µh) Capacitance (pf Max) DC Resistance (Ω Max) Table 2 - TP Transformer Sources Vendor HALO HALO BEL PULSE PULSE Part Number TG ND TG110-S050N2 S J9 H1102 H1089 TP TRANSMIT OUTPUT CURRENT SET LAN83C183 The TPO± output current level is set by an external resistor tied between REXT and GND. This output current is determined by the following equation where R is the value of REXT: I out = (10K/R) x I ref Where Iref = 40 ma (100 Mbps, UTP) = 32.6 ma (100 Mbps, STP) = 100 ma (10 Mbps, UTP) = 81.6 ma (10 Mbps, STP) REXT should be typically set to 10K Ω and REXT should be a 1% resistor in order to meet IEEE specified levels. Once REXT is set for the 100 Mbps and UTP modes as shown by the equation above, I ref is then automatically changed inside the device when the 10 Mbps mode or UTP120 / STP150 modes are selected. Keep the REXT resistor as close to the REXT and GND pins as possible in order to reduce noise pickup into the transmitter. Since the TP output is a current source, capacitive and inductive loading can reduce the output voltage level from the ideal. Thus, in actual application, it might be necessary to adjust the value of the output current to compensate for external loading. One way to adjust the TP output level is to change the value of the external resistor tied to REXT. A better way to adjust the TP output level is to use the transmit level adjust register bits accessed through the Ml serial port. These four bits can adjust the output level by -14% to +16% in 2% steps as described in Table 3 - Cable Configuration. 36

37 CABLE SELECTION The LAN83C183 can drive two different cable types (1) 100 Ω unshielded twisted pair, Category 5, or (2) 150 Ω shielded twisted pair. The LAN83C183 must be properly configured for the type of cable in order to meet the return loss specifications in IEEE This configuration requires setting a bit in the serial port and setting the value of some external resistors, as described in Table 3 - Cable Configuration. The Cable Type Select bit in Table 3 - Cable Configuration is a bit in the MI serial port Configuration 1 register that sets the output current level for the cable type. R TERM in Table 3 is the value of the termination resistors needed to meet the level and return loss requirements. The value for R TERM on the TPO± outputs is for the two external termination resistors connected between V DD to TPO±, the value for R TERM on the TPI± inputs is for the sum of the four series resistors across TPI±, as shown in Figures 1 through 3. These resistors should be 1% tolerance. Also note that some output level adjustment maybe necessary due to parasitics as described in the TP Output Current section. Table 3 - Cable Configuration Cable Cable Type Type Select Bit TPO± (16.7) 100 Ohm UTP, Cat 5 UTP R TERM1 = 50 Ω R TERM2 = 50 Ω 150 Ohm STP STP R TERM1 = 75 Ω R TERM2 = 75 Ω R TERM (Ω) TPI± R TERM3 + R TERM4 + R TERM5 + R TERM6 = 100 Ω R TERM3 + R TERM4 + R TERM5 + R TERM6 = 150 Ω TRANSMITTER DROOP The IEEE specification has a transmit output droop requirement for 100Base-TX. Since the LAN83C183 TP output is a current source, it has no perceptible droop by itself. However, the inductance of the transformer added to the device transmitter output as shown Figure 19 through Figure 21 will cause droop to appear at the transmit interface to the TP wire. If the transformer connected to the LAN83C183 outputs meets the requirements in Table 1 - TP Transformer Specification, the transmit interface to the TP cable will meet the IEEE droop requirements. FX INTERFACE General The FX interface is typically connected to an external fiber optic transceiver. The FX interface inputs are outputs are designed to drive 100 Ω differential loads. The FX interface can be directly coupled to either 3.3V or 5V fiber optic transceivers with minimum external components, as described in the following sections Connection to 3.3V Transceivers The schematic for a typical connection of the LAN83C183 to an external 3.3V fiber transceiver is shown in Figure

38 The 70 Ω and 173 Ω resistors on FXO± are used for 100 Ω termination and for biasing the LAN83C183 FX0± outputs to match the input range on the 3.3V fiber transceiver inputs. These resistors should be placed as close as possible on the PCB to the fiber optic transceiver inputs. In addition, the parasitic loading on FXO+ and FXO- should be kept to a minimum and matched as well as possible. The 127 Ω and 83 Ω resistors on FXI± and SD/nFXDIS are used for 100 Ω termination and for biasing the 3.3V fiber transceiver outputs to match the input range on the LAN83C183 FX inputs. These resistors should be placed as close as possible on the PCB to the LAN83C183 fiber inputs. In addition, the parasitic loading on FXI+ and FXI- should be kept to a minimum and matched as well as possible. In the 3.3V transceiver application, the SD_THR pin needs to be tied to GND, as shown in Figure 22 - Connection to 3.3 Volt Fiber OpticTransceivers. The SD/nFXDIS ECL trip level is determined by the SD_THR pin. The SD/nFXDIS internal buffer trip level needs to be set to V DD - and must be referenced to the 3.3V supply. Tying SD_THR to GND causes the device to internally set the ECL trip point on the SD/nFXDIS input buffer to V DD -1.3 and references it to the common 3.3 V supply. 38

39 Figure 22 - Connection to 3.3 Volt Fiber OpticTransceivers Connection to 5V Transceivers The schematic for a typical connection of the LAN83C183 to an external 5V transceiver is shown in Figure

40 Figure 23 - Connection to 5 Volt Fiber Optic Transceivers The 62 Ω and 263 Ω resistors on FXO± are used for 100 Ω termination and for biasing the 3.3V LAN83C183 FXO± to match the input range on the 5V fiber transceiver inputs. These resistors should be placed as close as possible on the PCB to the fiber optic transceiver inputs. In addition, the parasitic loading on FXO+ and FXO- should be kept to a minimum and matched as well as possible. The 83 Ω, 57 Ω and 68 Ω resistors on FXI± and SD/nFXDIS are used for 100 Ω termination and for biasing the 5V fiber transceiver outputs to match the input range on the 3.3V LAN83C183 FX inputs. These resistors should be placed as close as possible on the PCB to the LAN83C183 fiber inputs. In addition, the parasitic loading on FXI+ and FXI- should be kept to a minimum and matched as well as possible. 40

41 In the 5V transceiver application the SD_THR pin needs to be tied to V DD -1.3V, which can be done with an external resistor divider as shown in Figure 23. The SD/nFXDIS ECL trip level is determined by the voltage on the SD_THR pin. The SD/nFXDIS internal buffer trip level needs to be set to V DD -1.3V and must be referenced to the fiber transceiver 5V supply. Using a resistor divider from the fiber transceiver 5V supply to generate the voltage for the SD_THR pin references the SD/nFXDIS ECL trip level to the transceiver 5V supply. This allows the LAN83C183 SD/nFXDIS ECL trip level to track the supply variations of the fiber transceiver allowing direct connection of the fiber transceiver signal detect output to the LAN83C183 SD/nFXDIS input, as shown in Figure 23. Disabling the FX Interface The FX interface can be disabled by tying the SD/nFXDIS pin to GND, as shown Figure 19 through Figure 21. When the FX Interface is disabled, the TP interface is enabled, and vice versa. 41

42 9. Ethernet Specific Guideline Summary This chapter will give the board layout Designer a bullet list of items that should be considered to implement an EMI compliant design. The designer may wan to to use this list as a check off to determine if all considerations have been addressed. 1. Analog and ground planes should be connected at only one location. You may also want to have via s available at other locations on the board if a design change is necessary. 2. The Analog and Ground Plane connection should be as close to the power source, connector or Dc- Dc converter as possible. 3. Analog power and signals should be over the Analog Ground. 4. Digital power and signals should be over the Digital Ground. 5. Power distribution planes must be layer to Layer and as close to each other as possible. This allows the most efficient utilization of distributed capacitance for high-speed digital and analog signals. 6. Keep the Digital clock as far away from the Analog inputs, traces and voltage pins. 7. Bypassing and decoupling capacitors should be as close to the IC pins as possible as well as proper use and value of decoupling capaciters (decoupling capaciter for every chip). 8. Partition the board layout to keep the Analog and Digital portions of the design as far from one another as possible. 9. Have separate Analog and Digital ground planes, which may be on one layer attached at one location (see above). 10. For boards with more than two layers (This is the case in the SMSC Carbus 83C175 multi-function Reference Design, see the next chapter), do not overlap analog and digital planes. 11. In case where you have magnetic de-coupling devices, as in the case of the Ethernet transceiver, do not run the Analog or Ground planes beneath it. 12. Areas between Digital traces should be filled, when possible with copper, which should be attached to the Digital ground plane. Similarly, the Analog traces should be filled with copper, which should be attached to the Analog Ground Plane. 13. Use buffers, whenever possible for digital signals directly to or from the connectors which go off the board. 14. The use of terminators on signals with long data paths is desirable. 15. Unused inputs should be tied to a stable logic state (logic 0 = 5v, 1=0v). 42

43 10. Design Example - Ethernet + Modem PC Card In this section, the Ethernet + Modem design based on the SMSC LAN83C175 EPIC 10/100 Cardbus Fast Ethernet Controller is used as an example to illustrate desgn practices involved in providing good EMC compliance.. Figure 24 SMSC LAN83C175 10/100 Ethernet Plus V.90 Modem Multi Function Cardbus Design on page 44 shows the block diagram of the SMSC s Ehternet + Modem reference design based on the SMSC LAN 83C175 Dual function 10/100 Fast Ethernet Controller. This design is available to developers designing with the SMSC LAN 83C175. This design has used the EMC design methodology discussed in this document. The design utilizes the SMSC LAN 83C175 as both the Ethernet Media Access Controller (MAC) as well as the interface chip to the second function which in this case is a modem. This design and associated layout utilizes the guidelines described in this application note. Because size and area are critical in the design layout process of PC Card desgins, EMC design is even more complicated. There are however many similarities to adapter (PCI) or riser card designs and as a result, the layout of this design would be applicable in all cases. This design uses several power planes. The PC Card architecture requires that CardBus cards operate on a 3.3V supply provided by the host. Because some devices specified in the schematic require 5V, a DC-to-DC converter is required in this design. This requires multiple power planes. The multiple voltage rails are required when different devices require different power levels. 43

44 3.3V 3v to 5v DC-DC COnverter Modem Data Bus MD[0:7] Modem Address Bus MA[A0-A10] 5V Control 32 bit Cardbus 5V MD[0:7] MA[0:10] nwr.nrd,nromsel MD[0:7] MA[0:10] Interrupt/Modem Ring ncs,nwrite,nread Cardbus Connector 5V SMSC LAN83C175 10/100 Ethernet Media Access 256K Flash for CIS (Card Information Structurre) Controller SMSC LAN83C V 10/ MII 100 Mbps Fast Ethernet Physical Layer (PHY) Device Modem Micro Controller Unit (Rockwell LU ) Data CLK 5V Addr./Data 5V 5V Modem Speech Codec (R ) Modem Data Pump (R685) 1M (128kx8) RAM Modem Speech Codec (R ) GSM Phone Cell Phone Tel Line 2k Serial EEPROM 1M (128x8) ROM/ FLASH Modem Firmware Transformer RJ45 SMSC LAN83C175 10/100 Ethernet Plus V.90 Modem Multi Function Cardbus Design Figure 24 SMSC LAN83C175 10/100 Ethernet Plus V.90 Modem Multi Function Cardbus Design 44

45 SMSC LAN83C175 Cardbus Dual Function Reference Schematics This section describes the SMSC LAN83C175 Dual Function Reference Design. This design is an example of a Cardbus Multi-Function Ethernet plus v.90 Modem solution. This design has been certified by the FCC with a class B rating. As will be discussed, many of the EMI compliance issues discussed have been used in this design in order to achieve FCC Class B Compliance. The schematics shown below is a Production Ready design. The schematic consists of 8 pages. Page 1 is intentionally not shown since it is just the cover page. Page 2 shows the high level Cardbus to LAN Phy interface. The Flash ROM that maintains the CIS (Cardbus Information Structure) as well as other non-volatile information. This page also shows the 25 MHz clock logic that is required to support the 10/100 Ethernet MAC. The schematic also shows the high level Cardbus interface to Modem DSP interface. The Modem DSP/Micro. That is unsupported in this design is the Rockwell Semiconductor/Connexant L2600 Chip set. Page 3 of the SMSC LAN83C175 LAN plus Modem design is the pin signaling of the LAN83C175. Note that the Modem Address bus MA[0:15] lines do not utilize MA15. Also note that the lower three address lines have pull-downs required for configuration select. Please refer to the SMSC 83C175 Data Sheet for additional information. Page 4 shows the 10/100 Ethernet Phy Block. This part of the design is an area that needs to be focused on to achieve a compliant EMI function. The importance of Ground and Power isolation discussed in the previous chapter must be adhered too to achieve low emissions. Page 5 describes the Modem DSP interface to the Modem DAA block on a different page. Note the DC- DC converter. This DC-DC converter is required since the Modem chip set is currently a 5V design. Since Cardbus is inherently a 3.3v interface, the DC-DC converter is required. Since the SMSC LAN 83C175 supports a separate Cardbus, Modem and Ethernet PHY Power Rail interface, the LAN83C175 can support mixed Power Rail designs easily. This is an important feature. It is intended in the next generation of designs that future Modem Designs will support 3.3v. However, it is expected that in the future, there will still be designs supporting Wide Area Access (WAN s) that will require 5v Support. Page 6 shows the Modem Data Pump to Modem DAA interface. Page 7 shows the pin signaling of the Modem Data Pump. Page 8 describes the MODEM DAA interface block. This block has a lot of discrete components and placement of these components is important. Please refer to the Rockwell / Connexant Modem Application notes available from their web page for more information. 45

46 A Cardbus 10/100 Ethernet + 56Kbps Modem - MAIN BLOCKS Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y B 2 8 Thursday, April 02, 1998 Title Size Document Number Rev Date: Sheet of PAGE_04 LAN_PHY RCLK RX_ERR CRS TXEN TCLK DV COL RXD[0..3] ANEG TXD[0..3] MDIO MDC PWRDWN RST# /CABLE_DET LINK# 25MHz PHY_INT# PAGE_03 LAN_MAC CAD[0..31] CPAR CBE0# CBE1# CBE2# CBE3# CIRDY# CTRDY# CFRAME# CDEVSEL# CSTOP# CPERR# CCLKRUN# CBCLK CSERR# CINT# CGNT# CREQ# CBLOCK# CAUDIO STSCHG CRST# TX_CLK MCLK TX_EN RX_CLK RX_DV RX_ERR MDATA CRS COL LNK# TXD[0..3] RXD[0..3] A[0..14] D[0..7] RD# WR# ROMCS# PHYRST# PHY_PWRDWN# IREQM MODCS# MOD_PD MOD_FPD# RINGIN 25MHz_IN ANEG CABLE_DET# MODRST# RINGOUT MODRDY AUDIO_IN PHY_INT# PAGE_05 MODEM_MICRO D[0..7] A0 A1 A2 RD# WR# CS# PD# RESET# FET_PD# INT READY# SPKR RINGIN RINGOUT VCC VCC MOD_VCC VCC 25MHz RXD[0..3] TXD[0..3] 25MHz FETPWRM A9 D1 D4 A7 A11 D0 A0 A3 A8 D2 A1 A5 A12 A14 MODCS# D6 D7 D3 A[0..14] A13 D5 A10 D[0..7] A6 A2 A4 INT MODRDY MOD_RST# RINGOUT PWRDWNM WR# RD# CAD20 CAD19 CAD2 CAD[0..31] CAD31 CAD16 CAD15 CAD9 CAD8 CAD14 CAD11 CAD6 CAD0 CAD24 CAD30 CAD26 CAD21 CAD29 CAD25 CAD23 CAD27 CAD4 CAD28 CAD12 CAD5 CAD18 CAD13 CAD10 CAD7 CAD3 CAD17 CAD22 CAD1 ROMCS# A0 A1 A2 WR# R5 100R R2 10K R3 100R J1 CON68_CARDBUS GND CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# VCC VPP1 CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 RFU CCLKRUN# GND GND CCD1# CAD2 CAD4 CAD6 RFU CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 RFU CBLOCK# CSTOP# CDEVSEL# VCC VPP2 CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CAUDIO CAD28 CAD30 CAD31 CCD2# GND CCBE3# CSTSCHG GND GND GND GND GND GND GND GND + C1 10u R1 10K FB1 BLM21B102SPT C4 u1 R94 0 R96 0 R95 0 U3 NC7SZ04M U2 M214TGN GND/INH OUT PWR R104 0 C3 u1 U1 AT29LV A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WE D0 D1 D2 D3 D4 D5 D6 D7 VCC GND R12 10K R4 0 R If U1 is AT29LV256, populate R94 and R96. If U1 is AT28LV64, populate R95.

47 A Cardbus 10/100 Ethernet + 56Kbps Modem - LAN MAC Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y B 3 8 Thursday, April 02, 1998 Title Size Document Number Rev Date: Sheet of VCC VCC MOD_VCC CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 CAD11 CAD13 CAD14 CAD12 CAD15 CAD16 CAD17 CAD18 CAD19 CAD21 CAD22 CAD20 CAD23 CAD24 CAD29 CAD31 CAD26 CAD25 CAD30 CAD28 CAD27 TXD3 TXD2 TXD1 TXD0 RXD3 RXD2 RXD1 RXD0 D0 D1 D3 D2 D6 D7 D5 D4 A0 A1 A3 A2 A4 A5 A7 A6 A8 A9 A11 A10 A14 A12 A13 R9 6K04 1% R6 10K R7 10K R8 10K U4 SMC83C175 - EPIC/C PHYRST# RESETM# PHY_PWRDWN# MEMRD# FETPWR_PHY RDYM MA0 IREQM MEMWR# POWERDWNM NC FETPWRM CSM# RINGIN MA1 RINGOUT ROMCS# AUDIOIN MD0 MA2 NC MA3 VDDMOD MA4 NC MA5 MD1 MA6 NC MA12 MA11 MA10 MA9 MA8 MA7 VDD NC MD2 NC VDDPHY NC MA15 MA14 MA13 MD3 NC VDDMOD NC MD4 NC VDD NC MD5 NC VDDMOD NC MD6 NC VDD MD7 VDDMOD VSS VDDMOD VDD VDDPHY VDDPHY VDD MII_TXD3 VDD VDDPHY VDD VDDPHY VSS VDD VDD MII_TXD2 VDD VDD VSS VDD VDD MII_TXD1 VDD VDD VSS VDD VDD MII_TXD0 VDD VDD VSS VDD VDD VSS VDD VDD MII_TX_CLK VDD VDD VSS VSS VSS MII_RXD0 VSS VSS VSS CBE0# VSS VSS VSS MII_RXD1 VSS CAD0 VSS MII_RXD2 VSS CBE1# MII_RXD3 CAD1 MII_RX_CLK CBE2# MII_RX_ERR CAD2 MII_TX_EN VSS CBE3# VSS MII_RX_DV VSS CAD3 VSS MII_CRS VSS CAD4 VSS MII_COL VSS CAD5 VSS MII_MDATA VSS CAD6 VSS MII_MCLK VSS CAD7 VSS CAD8 VSS CAD9 VSS CAD10 VSS CAD11 VSS CAD12 VSS CAD13 VSS CAD14 VSS CAD15 VSS CAD16 VSS CAD17 VSS CAD18 VSS CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31 CPAR CREQ# CGNT# CIRDY# CTRDY# CFRAME# CDEVSEL# CSTOP# CINT# CSERR# CPERR# CBCLK CCLKRUN# RST# STATCHG CBLOCK# CAUDIO BIAS ZENER CLK25IN TEST X20 694EN# 694LNK# GPIO1 GPIO2 IN GND OUT U5 MAX C8 u1 C6 u1 C5 u1 C7 u1 C9 u1 C10 u1 C12 u1 C11 u1 CAD[0..31] CPAR CBE0# CBE1# CBE2# CBE3# CIRDY# CTRDY# CFRAME# CDEVSEL# CSTOP# CPERR# CCLKRUN# CBCLK CGNT# CBLOCK# TX_EN TXD[0..3] A[0..14] RD# WR# ROMCS# PHYRST# MODCS# MODRST# MOD_FPD# 25MHz_IN CREQ# CINT# CRST# CSERR# CAUDIO STSCHG LNK# RXD[0..3] RX_CLK RX_ERR TX_CLK RX_DV CRS COL IREQM RINGIN MDATA D[0..7] MCLK MOD_PD RINGOUT MODRDY AUDIO_IN PHY_INT# CABLE_DET# ANEG PHY_PWRDWN#

48 A Cardbus 10/100 Ethernet + 56Kbps Modem - LAN PHY Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y B 4 8 Friday, February 12, 1999 Title Size Document Number Rev Date: Sheet of VCCA VCCB VCC VCC VCC VCCB VCCA VCCA VCCB VCC VCC VCCB VCC VCC LED_10 LED_RX RXD2 RXD3 RXD1 RXD0 RXD[0..3] TXD[0..3] TXD0 TXD2 TXD3 TXD1 LED_100 LED_100 LED_TX LED_TX LED_RX LED_10 T2 TG110-SO50P S+ SC S- PM+ PMC PM- PC C15 u1 C17 u1 C22 u1 C16 u1 L1 10uH C18 u1 J2 RMC-EA16LMY-OM00-A L2 10uH FB2 BLM21B102SPT FB3 BLM21B102SPT R18 47K R21 9K76 1% T1 TG110-SO50P S+ SC S- PM+ PMC PM- PC C24 u1 R15 100R 1% C20 u1 C19 u1 C21 u1 R20 10K R10 75R R14 75R C p 1210 R11 75R R13 75R R16 49R9 1% R17 49R9 1% FB19 BLM21B102SPT R FB4 BLM21B102SPT U8 78Q2120CGT MDC RXD3 MDIO TXD0 TXD1 TXD2 RST RXD0 RXD1 RXD2 TXOP RXER RXDV TXER TXEN RXCLK TXCLK CRS COL PWRDN CTSL ANEGA TECH2 TECH1 TEST TECH0 PCSBP ISO ISODEF PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 LKPS TIOP TION VNA VNB VNC VNC VNS VNS VND VND VND VND VPA VPB VPC VPC VPD VPD VPD VPD TXON RXIP RXIN LEDFDX LEDBT T4 LST41 LST40 LEDL LEDTX LEDRX LEDCF LED100X GPIO1 GPIO0 BLW EQR RVCO TVCO RIBB CKIN XTLP XTLN TXD3 INTR FB20 BLM21B102SPT U9 NC7SZ04M5 2 4 R105 4K7 RCLK RX_ERR CRS TXEN TCLK DV COL RXD[0..3] ANEG TXD[0..3] MDIO MDC LINK# RST# /CABLE_DET 25MHz PHY_INT# PWRDWN Pin 17 is shield ground tab

49 A Cardbus 10/100 Ethernet + 56Kbps Modem - Modem Micro. Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y B 5 8 Thursday, April 02, 1998 Title Size Document Number Rev Date: Sheet of PAGE_06 MODEM_BLOCK CELBSY DPSEL- READ- WRITE- D[0..7] A[0..4] DPIRQ MRDY- RINGOUT SPKR OH- STAT syclk VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 MOD_VCC VCC5 VCC VCC5 VCC VCC MA17 MD7 MA13 MA10 MA0 MD6 MA15 MA16 MA7 MA5 MA11 MA9 MA3 MA2 MD2 MA14 MA1 MD0 MD3 MD4 MD1 MD5 MA8 MA6 MA12 MA4 MD6 MD4 MD1 MD3 MD7 MD5 MD0 MD2 MA4 MA6 MA12 MA9 MA7 MA0 MA13 MA5 MA7 MA15 MA2 MA4 MA2 MA12 MA10 MA14 MA11 MA1 MA8 MA0 MA9 MA10 MA16 MA11 MA8 MA3 MA6 MA3 MA1 MA5 MA14 MA13 MA[0..16] MA17 STAT OH- DPIRQ CELBSY- MD[0..7] DPIRQ READY- OH- STAT D[0..7] D5 D2 HINT RESET- READY- D7 D6 A1 D3 MPWRDWN D1 D4 A[0..2] MCE- D0 A0 A2 MD7 MD6 MD2 MD0 MD3 MD4 MD1 MD5 MA15 MA16 MIOWR- MIORDsyclk syclk CELBSY- C30 u1 C25 u1 L3 4u7 D1 MBR0520L C28 1u5 ASIZE R28 100K R29 100R Y MHz C34 18p R27 33R R24 47K R93 0 U10 L HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HA2 HCS- HWR- HRD- HINT RESET- STPMODE- NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC ES1SEL- ES0SEL- DAA/GSM GSMRXD GSMTXD CELCLK/GSMINP0 CELBSY-/RXDCLK CELDATA DAA/CELL RLY1-/CTRL0 RLY2-/CTRL1 RLY3-/CELBSY RLY4- LCS RINGD D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 WR- RD- DPSEL- ROMSEL- RAMSEL- READY- DPIRQ NVMDATA NVMCLK TST- PSC NMI- VDD VDD GND GND GND GND GND GND XTLI XTLO U14 MAX IN GND FB SHDN SS LX OUT PGND R98 10k R99 10k U30 NC7SZ04M U TSOP D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CS WE OE A15 A16 CS VCC GND NC R40 4K7 R23 0 C31 4u C27 u1 U11 29F020TSOP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE O0 O1 O2 O3 O4 O5 O6 O7 VCC GND A17 NC U15 24C A0 A1 A2 GND VCC TEST SCL SDA C32 10n C33 18p L6 4u7 R122 0 R123 0 RINGOUT SPKR RINGIN CS# INT A[0..2] READY# RESET# D[0..7] FET_PD# PD# WR# RD# Flywire between pin 40 and 43 is required for Rev A of the board

50 PAGE_08 PAGE_07 D[0..7] A[0..4] DPSEL- WRITE- READ- DPIRQ MRDY- RINGOUT SPKR syclk D[0..7] A[0..4] D[0..7] A[0..4] DPSEL- WRITE- READ- DPIRQ MRDY- RINGOUT SPKR syclk RIN TXA1 TXA RIN TXA1 TXA2 DATA_PUMP CELBSY STAT OH- DAA RING_DETECT STAT /OH R R R Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y Title Cardbus 10/100 Ethernet + 56Kbps Modem - Modem Block Size Document Number Rev B A Date: Thursday, April 02, 1998 Sheet 6 of 8 50

51 VCC R33 20k L4 10uH 1 C38 u1 AGND + C37 10u ASIZE syclk VCC5 1 R k 1 R k 1 R R AVCC TIRO2 CLKIN TXD 75 CTS 76 RLSD TDCLK SYCLK SR4OUT MTXSIN SR3OUT VTXSIN SR4IN VRXOUT SR3IN MRXOUT YCLK XCLK MCLKIN VCLKIN CLKOUT SA1CLK MSTROBE IA1CLK MSCLK MCNTRLSIN SR1IO VSTROBE SA2CLK VCNTRLSIN SR2IO GPO0 RDCLK XTCLK RXD AVAA AVDD AVDD VDD VDD VDD VDD U VGG R R NOXTL RI XTLO XTLI IASLEEP SLEEPO RIN TXA1 TXA2 RINGD VREF VC TELIN TELOUT RLYB RLYA VCC5 C36 u1 R R 1 2 Y MHZ C43 u1 C46 u1 C41 10p C39 10p AGND C40 L p + C42 10u ASIZE + C45 10u ASIZE 4.7uH RINGOUT RIN TXA1 TXA D[0..7] A[0..4] DPSEL- WRITE- READ- MRDY- D[0..7] A[0..4] 2 R78 10K DPIRQ 1 R80 20K A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7 R R42 C47 u1 X7R 10K 10K RTS DSR DTR IRQ D0 D1 D2 D3 D4 D5 D6 D7 RS0 RS1 RS2 RS3 RS4 CS WRITE READ RES1 RES2 DP56K_144PIN in TQFP144 package GND GND GND AGND AGND GND GND MICM MICV PLLVDD PLLCAP PLLGND SPKMD 24 SPK SR2CLK VSCLK GND GND GND1 GND2 GND3 GND GND GND DP56K_144PIN C48 u1 VCC5 SPKR Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y AGND Title Cardbus 10/100 Ethernet + 56Kbps Modem - Data Pump Size Document Number Rev B A Date: Thursday, April 02, 1998 Sheet 7 of 8 51

52 VCC5 C86 u33 200V X7R 1825 FB17 VCC5 J3 RING_DETECT /OH STAT RIN TXA1 TXA2 TXA1 /OH R106 47k 1/16W 5% 0603 R TXA2 R116 R 0603 R113 10K 0603 VCC5 R109 1k R112 10K D8 3 U33 TS117 FORM A 8SOP150 SSR/OPTOCOUPLER C90 10n CMPZDA4V3 CAP CERAMIC 0603 ZENER DUAL T C88 CAPACITOR POL ASIZE R115 47K 1/16W 1% 0603 C89 10n CAP CERAMIC 0805 C u C92 + 6u R119 6R19 1/10W 1% D6 DUAL ZENER C93 CAPACITOR POL ASIZE + R107 8k2 1W 2512 R K SSR_TIP 2 Q3 CZT2000 3SOT223 R118 27R 1/10W 1206 BLM21B102SPT FB18 BLM21B102SPT RV1 P3100SA SIDACTOR DO-214AA D CMPD7000 SOT23 CMPD D9 3 R110 0R 1210 C pf 0805 R HONDA 16 Pin 17 of J3 is Frame GND Standard Microsystems Corp. 300 Kennedy Drive Hauppauge N.Y Title Cardbus 10/100 Ethernet + 56Kbps Modem - DAA Size Document Number Rev B A Date: Friday, February 12, 1999 Sheet 8 of 8 52

53 SMSC LAN83C175 Cardbus Dual Function Reference Layout This section will discuss layout issues regarding implementing a Cardbus Dual function 10/100 MB/s Ethernet plus V.90 modem design. These plots are included to provide an example of how to layout a PCB for LAN and modem functions. This design achieved FCC Class B and Part 68 certifications. This design consists of six layers. There is a power and Ground layer and four (4) signal layers Power Layer The layout plane shown below in Figure 25 - LAN83C175 Ethernet plus Modem Power layer shows the power layer of the board. The white area of the Power Layer indicate Copper and the Black portions show a void. Figure 25 - LAN83C175 Ethernet plus Modem Power layer Note that the Power layer shown above has no layer under the Analog Ethernet Transceiver portion o the board as well as under the Ethernet Magnetics device The Cardbus signaling area of the board also does not have a power plane. This method is consistent with the Guidelines defined in the Ethernet Specific Guideline Summary Ground Layer The layout plane shown below in Figure 26 - LAN83C175 Ethernet plus Modem Ground Layer describes the Ground Layer of the board. Again, the white area of the Ground layer show Copper and the Black indicates a void. 53

54 Figure 26 - LAN83C175 Ethernet plus Modem Ground Layer As in the Power Layer shown above, note that the Ground layer shown in Figure 26 - LAN83C175 Ethernet plus Modem Ground Layer above, has no layer under the Analog Ethernet Transceiver portion of the board. This is also true under the Ethernet Magnetics device The Cardbus signaling connector area of the board also does not have a power plane. This method is consistent with the Guidelines defined in the Ethernet Specific Guidelines Summary section. For optimum EMI performance, Power Distribution planes, as shown above, should be as close to each other to provide maximum distributed capacitance for decoupling high speed signals. 54

55 Layer 4 ing Figure 27 - Bottom Side ing The layout, shown in Figure 27 - Bottom Side ing above shows the Bottom Side of the PC Card Reference design signal routing layer. Overall performance is enhanced when PCB trace lengths are reduced as shown. This Improves return loss performance due to reduced capacitance. Emissions should also improve as short traces are less susceptible to radiated system noise and will be less likely to generate noise. 55

56 ing Bottom Side Figure 28 - Bottom Side ing Layer 56

57 ing Top Side Figure 29 - TopSide ing Layer 57