EMI. Chris Herrick. Applications Engineer

Transcription

1 Fundamentals of EMI Chris Herrick Ansoft Applications Engineer

2 Three Basic Elements of EMC Conduction Coupling process EMI source Emission Space & Field Conductive Capacitive Inductive Radiative Low, Middle & High Frequency Low & Middle Frequency LC Resonance High Frequency EMS Immunity

3 Controlling EMI EMI source Emission Coupling process EMI Filters Shields Conduction Space & Field Conductive Capacitive Inductive Radiative Low, EMI Middle Filters & High Frequency Low Shields & Middle Frequency Shields LC Resonance High Shields Frequency Immunity EMS

4 PCB Noise Sources Intentional Signals Emissions from intentional signals include loop-mode and common-mode sources. Unintentional Signals ( more than 90% of EMI ) Emissions i from unintentional ti signals include common-mode, crosstalk coupling to I/O traces (both PCB and IC level), power planes, and above board structures. *Reference from PCB Design for Real-World EMI Control, Bruce Archambeault

5 Intentional Signals Focus on Clock and High Speed Signals Stripline not necessarily better than Microstrip Examine Clock Harmonics Common Mode Conversion SCD11=0.5*(S11-S13+S31-S33) SCD21=0.5*(S21-S23+S41-S43)

6 Unintentional Signals Crosstalk is a big concern Beware the low speed nets; use post-layout analysis to scan for unintended coupling Coupling may be direct, through intermediate metal or even from plane cavities Common mode will always exist Don t neglect the overall plane impedance

7 Loop Mode & Common Mode Noise A PC Board & Cables Loop mode current A victim device A Driver & Receiver by AC Analysis of Q3D Extractor Differential mode current flows --- Loop Common mode current flows --- Open We can see Common mode current is more serious than Normal mode. Common mode current

8 Antenna theory -A Differential mode current flow Loop antenna theory -A Common mode current flow Dipole antenna theory E = (f r 2 AI) sin θ E = 7 4π 10 ( f Il) sinθ r A : area of the loop θ r : distance θ r Illustration of a loop antenna I Length :l I Illustration of a dipole antenna FCC B level Mag. E limit 3m Mag. E( Loop antenna) : 20mA Mag. E( Dipole antenna) : 8uA

9 EMC Design Flow Impedance Analysis Resonance Analysis Signal Extraction Ensure a low impedance as seen by active parts Change stackup, plane cutouts t and decoupling as necessary Emissions Analysis Enclosure Simulation

10 Decoupling Capacitor Decoupling Capacitor on Package Chip Via Va On-chip Pwr/Gnd Ball Bonding VRM Power/Ground Wire Bonding Ball Bonding VRM Package P/G Network PCB P/G Network Chip Decoupling Decoupling Capacitor Capacitor on Chip on Package Decoupling Capacitor on PCB Bulk Capacitor Near VRM

11 Decoupling Impedance of PDN 1uF 0.1uF 0.01uF Bare PCB 10uF Total PDN

12 Plasma Screen Example Changed Return Path Widened section of GND plane Added decoupling Capacitors GND GND Old model New model Impedance test port near C3,4,5

13 Impedance Plot Impedance : Old model Impedance New model

14 EMI Test Results : Old model CISPR spec.

15 EMI Test Results : New model

16 EMC Design Flow Impedance Analysis Resonance Analysis Ensure power planes do not resonant in critical locations Change stackup, plane cutouts and decoupling as necessary Signal Extraction Emissions Analysis Enclosure Simulation

17 Managing Resonances Even though resonances ALWAYS exist, you don t need to excite them: Keep them away from Clock harmonics Examine Via Transitions Avoid routing near splits Move discrete parts

18 VCC12 Z MHz 18

19 EMC Design Flow Impedance Analysis Resonance Analysis Signal Extraction Emissions Analysis Ensure signals meet required bandwidth Change routing as necessary Enclosure Simulation

20 Image Plane Violations Always Consider Return Current Path RF current return path Capacitor bridging the moat to transfer RF currents between partitions Signal Trace Moat or slot in ground plane

21 EMI Reduction using Ferrites Insert High Q Ferrite Insert Low Q Ferrite Without Ferrite Internal Clock Line

22 EMI Test Results Before Ferrite After Ferrite

23 Clock Distortion

24 Clock Distortion

25 Clock Distortion

26 Clock Distortion

27 Clock Distortion

28 Clock Distortion

29 EMC Design Flow Impedance Analysis Resonance Analysis Signal Extraction Emissions Analysis Enclosure Simulation Ensure EMI is at acceptable level Optimize previous three simulations

30 Full Channel Analysis DC Supply 0 A R563 R C /datarate R558 R inn inp Vcc Vss 0 outn outp diffout_probe A U1_8VCC_1GND U1_pair1_neg U1_pair1_pos SIwave Model VCC_main U2_1VCC_1GND U2_pair1_neg U2_pair1_pos A inn inp Vcc Vss 0 outn outp diffout_probe Load R545 R V475 V541 Differential PRBS 0

31 Real Drivers as Noise Source MaxE Radiated from PCB PCB Data-Line Source spectrum

32 Near-Fields V V High Z at 137 MHz Low Z at 50 MHz

33 EMC Design Flow Impedance Analysis Resonance Analysis Signal Extraction Emissions Analysis Enclosure Simulation Test performance of different enclosures Iterate design as necessary

34 Linking EMI Source with Shield A noise analysis by SIwave A excitation source SIwave to HFSS HFSS to HFSS A ECU analysis by HFSS A EM analysis by HFSS

35 A noise source and a cable 310 MHz Impedance Peak on PCB A cable

36 Conclusions It s easiest to control EMI at it s source Prevents Emission and Self Interference EMC is comprised of good PI and SI Simulating throughout the design cycle can help you avoid trouble in the chamber