Intro. to PDN Planning PCB Stackup Technology Series

Transcription

1 Introduction to Power Distribution Network (PDN) Planning Bill Hargin In-Circuit Design Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane Capacitance 4. Conclusion/Demo/Wrap-up 2-1

2 About the Presenter High Speed PCB Design Author/co-author of a dozen articles on high-speed design Hundreds of webinars, seminars, and workshops including a Fundamentals of High-Speed Design course that has been taken by over 10,000 engineers in more than 30 different countries HyperLynx Product Marketing Director PADS Software Director of International Business Development Mentor Graphics High-Speed Marketing Manager Director of Business Development, System-Level Engineering 3 Review: Steps in High-Speed PCB Stackup Planning 1. Determine how many signal layers are needed 2. Determine how many power planes are needed Distribute Power and Ground 3. Arrange signals and planes accordingly Partner planes for signal layers Parallel plate capacitance between Power and Ground Select dielectric materials 4. Set signal height above planes for crosstalk requirements 5. Set trace widths to meet impedance goals Differential signals, in particular 6. Set plane spacing to meet capacitance requirements 7. Set spacing between signal layers to meet overall thickness 4-2

3 PDN Design: Why should I care? Today s high-performance processors with sub-ns switching speeds use low DC voltages, drawing high transient currents at high clock frequencies Low output-buffer impedances, and simultaneous bus switching (SSO) cause high transient currents in power and ground planes, degrading product performance and reliability This can result in intermittent signal integrity issues, and many EMC failures are caused by excessive noise (SSN) on the PDN coupling into external cables 5 Power Integrity Power Integrity analysis can be broken into three broad categories #1: Pure power distribution analysis I.e., PDN or Power Distribution Network planning One of the most significant hardware-engineering challenges today #2: Mixed SI/PI simulation #3: Extraction of models for external simulators A legitimate need since there s no such thing as a panacean, one-tool-solves-all-problems solution High-Speed Update - User2User, March 2007, Mentor Graphics 6-3

4 Objective of the PDN Bypass networks support current surges that are beyond the short-term supply capability of the VRM Distribute power (and ground) with an acceptable level of rail noise Typically less than 5%, for core logic switching, I/O switching and internal signal layer transition switching A typical DDR3 design may contain 5-6 different power supplies This translates to keeping the impedance of the PDN, as seen by the chip die, below a target impedance value across the typical operating frequency of the product Designing a power delivery network with Z PDN under Z target over a wide frequency band may not be possible in all designs The process can also be expensive, requiring tradeoffs to reach a balance between cost and performance 7 Simplified PDN View and Ripple Voltage A PDN has an impedance (Z PDN ) associated with the path from the VRM to each high-speed IC The magnitude of noise ( voltage ripple or rail noise ) on a power rail is proportional to the PDN impedance (Z PDN ) and the transient current (I transient ) draw from the rail V ripple = I transient x Z PDN Z PDN Die Load V ripple can be reduced by reducing Z PDN I transient is application-specific and determined by the signal switching pattern V VRM I transient 8-4

5 PDN Target Impedance: Z target The PCB part of Z PDN is within your control To make sure that Vripple (noise) is within spec, Z PDN should be designed so that it s below a specific target impedance, Z target Z target can be defined as: Z PDN Die Load V VRM I transient Where MaxTransientCurrent is the transient current estimated as a percentage of the total current draw 9 PDN Components, Cont d. Capacitance required to support simultaneous switching can be located in five places in a design On the IC die itself On the IC package The parallel planes of the PCB Discrete capacitors added to the power rails The output of the power supply module Source Right the First Time, Vol. 2, Lee Ritche,

6 PDN Components Each component added to the PCB lowers the impedance of the PDN at a particular frequency The PCB PDN network contains the following: VRM, or Voltage regulator module Decoupling capacitors Parasitics from power/ground plane spreading, and BGA vias Plane capacitance An illustration of the resonant frequencies of various PDN components Source PDN Planning, Barry Olney, ICD, PCB Magazine, May 2012 The Topology of a PDN VRM Model Bulk Bypass Caps Decoupling Caps Planar R, L, C Spreading Inductance Die BGA Via As with all aspects of stackup planning, the PDN design should be optimized before a single IC is placed on the board, and before a single trace is routed Source PDN Planning, Barry Olney, ICD, PCB Magazine, May

7 3 Most Important things in a PDN Z PDN Z L C F Z L C 1. Inductance 2. Inductance 3. Inductance And enough capacitance to lower the impedance at low frequencies Source: Steve Weir, IPBlox, cited in No Faith, by Eric Bogatin, PCD&M, August st Major PDN Component: Voltage Regulator Module (VRM) The first major component of the PDN is the VRM Typically a switching regulator that adjusts the current being supplied (via feedback) to keep voltage constant from DC to a few 100 khz For all transient events that occur at frequencies above this range, there is a time lag before the VRM can respond to the new demand Details vary by regulator DC to a few 100 khz Source PDN Planning, Barry Olney, ICD, PCB Magazine, May

8 Characterizing your VRM You need to start with the right Voltage Regulator Module (VRM), establishing a low impedance from DC to about 10 khz The right VRM depends on the target impedance, calculated from the supply voltage, max. current, transient current and max. allowed voltage ripple for each power plane Above this frequency the bypass capacitor network takes over A good PDN planning tool can help here DC to a few 100 khz 15 Source No Faith, Dr. Eric Bogatin, PCD&M, August nd Major PDN Component: Capacitors Tantalum bulk bypass capacitors and ceramic decoupling capacitors Supply instantaneous current (at different frequencies) to driver ICs until the VRM can respond Mitigate delays in the (on-board or remote) power supply circuit due to trace and driver-lead inductance Source PDN Planning, Barry Olney, ICD, PCB Magazine, May

9 2 nd Major PDN Component: Capacitors, Cont d. Bulk bypass capacitance typically provided by tantalum capacitors provides low impedance up to 10 MHz High-frequency decoupling is provided by ceramic capacitors up to several 100 MHz Every capacitor has an Equivalent Series Inductance (ESL), causing its impedance to increase at high frequencies Z L C 17 3 rd Major PDN Component: Plane Capacitance Above 200 MHz, high quality, low inductance capacitance is necessary to support the very fast switching transients associated with driving singleended transmission lines and rapidly changing IC core-supply currents This is provided by the capacitance formed by adjacent power and ground layers Source PDN Planning, Barry Olney, ICD, PCB Magazine, May

10 Reducing Z die VRM Model Bulk Bypass Caps Decoupling Caps Planar R, L, C Spreading Inductance Die BGA Via Chip-package design tradeoffs to reduce Z die Increase on-die capacitance Increase on-package capacitance Decrease package lead inductance Source PDN Planning, Barry Olney, ICD, PCB Magazine, May Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane Capacitance 4. Conclusion/Demo/Wrap-up 20-10

11 Decoupling Capacitor Overview A decoupling capacitor (decap) can be modeled as a series combination of R, L, and C R is the equivalent series resistance (ESR) L is the equivalent series inductance (ESL) C is the capacitor s capacitance Frequency response The equivalent circuit is an RLC series resonant circuit The self-resonant frequency (SRF) is determined by the circuit s L and C, which come from the materials and construction of the capacitor 159 ~ 1 GHz, where L=5 nh and C=.005 nf Note: Different equation from the recorded presentation I prefer this one! 21 High-Level, High-Speed Capacitor Strategy Capacitors reach their minimum impedance at their resonant frequency, which is determined by their capacitance and ESL To meet the target impedance at a particular frequency, a capacitance value is chosen that will resonate at the desired frequency, and have an impedance that is equal to its ESR (Equivalent Series Resistance) Then, a sufficient number of them are placed in parallel so that the parallel ESRs approach the desired target impedance 22-11

12 The Peanut Butter approach Some designers assume that by placing many different values of capacitors on the board, the entire frequency range is covered, and will have minimal impedance from DC to the max operating frequency Unfortunately, while it tastes pretty good, it s not that simple (and pretty high in calories) 23 Resonance and Anti-Resonance Resonant frequency(ies) 100nF and 1nF caps resonate at 16MHz and 170MHz Anti-resonance Where the 1nf and 100nF Z-plots intersect, they form a classic LC tank circuit (parallel resonance), raising the impedance This appears each time a different capacitor value is added to the network 100nF Caps are inductive 1nF Caps are capacitive here 24-12

13 3 Approaches to Decap Selection (Sept. 5 Webinar) Big V Typically, the largest value of capacitance for a given package size is used Multi-Pole Approach One capacitance value per decade (of capacitance) Many Pole Approach Three different capacitance values per decade Comparing the strategies These approaches provide a different impedance profile, and interact differently with the VRM at the low end, and board resonances on the high end The key is to focus on the phase at the system level 25 Source No Faith, Dr. Eric Bogatin, PCD&M, August 2006 If you like Simple Big V Simplest way to achieve low impedance over a given frequency range, and the most robust, relative to manufacturing variations and errors Typically, the largest value of capacitance for a given package size is used Smaller footprints minimize the inherent ESL of the capacitor For example, a 0.1nf 0201 has a lower ESL than a 0.1nf cap with a larger footprint for the same dielectric material and capacitor construction (E.g., 0402, 0603, 0805, etc.) 26 Source No Faith, Dr. Eric Bogatin, PCD&M, August

14 Decoupling Capacitor Position Capacitor ESL The mounted inductance or ESL of a cap has three components that describe the loop in which current must flow: [1] capacitor footprint; [2] distance from the plane; and [3] power plane spreading inductance The footprint (land pattern) for a capacitor consisting of via placement with respect to the pad, the length and width of connected Lower Inductance (Better) traces dominates the ESL 0402 capacitors with different fanout patterns End Vias Side Vias Double Side Vias Via in Pad 27 Inductance Budget and Decoupling Capacitor Position If the PCB consumes too much of the inductance budget, capacitor requirements grow exponentially Often a significant factor in high-performance systems Capacitor position The impact of decoupling cap position depends on the capacitors attached inductance compared to the spreading inductance in the planes If the PCB spreading inductance is a small % of your inductance budget, capacitor position doesn t matter Example: with caps on the same side of the PCB as the BGA and common power chevrons, and positions up to 0.5" from the BGA perimeter, the PCB inductance changes little and cap position is not critical 28 Source No Faith, Dr. Eric Bogatin, PCD&M, August

15 Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane Capacitance 4. Conclusion/Demo/Wrap-up 29 Interplane Capacitance Power to ground plane capacitance provides a near-ideal capacitor with very low series inductance and equivalent series resistance (ESR), reducing noise at extremely high frequencies Interplane capacitance needs to be calculated to establish the optimal use of the planes to create the ideal stackup C (pf) E r = Dielectric Constant C interplane = A = Area of the parallel planes (in 2 ) d = distance between planes (mils) 225 x Er x A d 30 Source The Perfect Stackup, Barry Olney, PCB Magazine, Nov

16 Interplane Capacitance The more capacitance, the better Good interplane capacitance can be achieved by using 3 or 4 mil plane spacing mils produces 225 pf/in 2 with the same E r 3-mil spacing results in 300 pf/in 2 with an E r of mil spacing would be even better, but you start playing with manufacturing tolerances and DBV 10-mil spacing will only produce 90 pf/in 2 And 20-mil spacing results in a dismal 45 pf/in 2 d (mils) C (pf/in^2) Source The Perfect Stackup, Barry Olney, PCB Magazine, Nov Review: Alternate ways to Stack Layers (10 Layer Example) Option 1: 6 Signal Layers, and only 1 Plane Pair Good for signal routing Fair for power (PDN) 90 deg. Stripline routing Option 2: 4 Signal Layers, and 2 Plane Pairs Fair for signal routing Good for power (PDN) 90 deg. Stripline routing = Prepreg = Laminate Option 3: 5 Signal Layers, and 1 Plane Pair Good for signal routing Fair for power (PDN) Good for crosstalk Most common Less common Backplanes Long bars are plane layers and short bars are signal layers

17 Planes aren t Perfect (just Forgiven) Ideally, a capacitively-coupled plane pair would provide a perfect capacitor with very low impedance between power and ground at very high frequencies (several 100 MHz and higher) But, they also insert inductance into the PDN, isolating ICs from Decaps Planes also act like wide, unterminated traces, reflecting energy from plane edges If this was for a 400 MHz DDR2 clock, we re not so concerned about the high impedance out above 1 GHz here 208 MHz=First resonance of the plane What? 33 Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane Capacitance 4. Conclusion/Demo/Wrap-up 34-17

18 Points to Remember The PDN impedance for today s high-speed products should be kept low and flat over a broad frequency range for proper product performance Levers include bulk bypass caps (up to 10 MHz) and decaps (up to 100s of MHz), parallel-plane capacitance (above 200 MHz) and on-die capacitance (to even higher frequencies) Lower inductance by placing capacitors close to power pins, placing the capacitors vias close to each other, and Z minimizing the length to the planes PDN Use interplane capacitance for 200 MHz and beyond, and pay attention to board-resonance effects See how it plays together w/ a PDN tool 35 F In-Circuit Design Software Download from: icd.com.au Stackup Planner The easiest tool available for planning Z0/Zdiff for 8+ layer boards Field solver for fast, accurate impedance calculations Multiple differential-signals on multiple layers Editable board-materials library DRCs ensure stackup validity PCB Interfaces in work PDN Planner PDN Planner analyzes the Voltage Regulator Module, PCB Substrate, and bulk bypass/decoupling capacitors to solve parameters for the desired effective impedance of the Power Distribution Network, across the product s entire frequency range Add an unlimited number of bulk bypass/decoupling capacitors Comprehensive, 300 Capacitor Library 36-18

19 PCB Stackup Planning in the Design Flow HARDWARE ENGINEER PCB DESIGNER FABRICATOR TEST Supported data formats include.stk,.csv, Clipboard, with PCB xlators on the way ICD Stackup Planner 37 In-Circuit Design PCB Design Services ICD s standard design process: 1. Stackup and PDN optimization 2. IC model acquisition and assessment 3. Pre-layout simulation eliminating signal integrity issues early, proactively constrain routing, optimizing clocks, and critical signal topologies and terminations prior to layout 4. Component placement according to pre-layout simulation 5. Trace routing according to simulation constraints, taking particular care of critical signals, differential pairs and flight times 6. Whole-board simulation, flagging Signal Integrity, Crosstalk and EMC hot spots 7. Validating termination values and strategies, reducing the negative impact of signal reflections 8. Interactive simulation of critical nets, looking at Signal Integrity, Crosstalk and EMC in detail 38-19

20 In-Circuit Design Plan B: Find and Fix Plan B Simulation Services: 1. Whole-board simulation of your PCB design analyzing Signal Integrity, Crosstalk, and EMC issues to FCC, CISPR & VCCI Class A & B standards 2. If we do find Signal Integrity, Crosstalk or EMC concerns, we can drill deeper, recommending appropriate solutions 3. Once the board is rerouted, as necessary, ICD will re-simulate the board, to verify that the changes produced the desired results Simulate twice - build once! 39 ICD Stackup Technology Series Schedule July 11 The Perfect Stackup: More than Impedance July 18 PCB Material Selection July 25 Impedance, Transmission Lines, and Termination August 1 Intro. to Power Distribution Network (PDN) Planning August 15 Material Selection for Multi-Gigabit SERDES Design August 22 Signal-Layer Selection: Microstrip, Buried Microstrip, Single and Dual Striplines August 29 Selecting a PCB Fabricator September 5 Decoupling/Bypass Capacitor Selection 40-20

21 References High Speed Digital System Design, by Hall, Hall, and McCall, 2000 No Faith, PCD&M, by Dr. Eric Bogatin, August 2006 PDN Network Design, PCB Magazine, by Barry Olney, In-Circuit Design, May 2012 Right The First Time, A Practical Handbook on High Speed PCB and System Design, Volumes 1 and 2, Speeding Edge, Aug and April 2007 Signal and Power Integrity Simplified, by Dr. Eric Bogatin, Prentice Hall, 2 nd Ed., 2009 The Perfect Stackup, PCB Magazine, by Barry Olney, In-Circuit Design, November