Electrical Test Vehicle for High Density Fan-Out WLP for Mobile Application. Institute of Microelectronics 22 April 2014

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Joel Heath
6 years ago
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1 Electrical Test Vehicle for High Density Fan-Out WLP for Mobile Application Institute of Microelectronics 22 April 2014

Challenges for HD Fan-Out Electrical Design 15-20 mm 7 mm 6 mm SI/PI with multilayer RDL on FO-WLP Signal path from chip to RDL to microbump/bga ball I/R drop analysis for Power Delivery Network

Measurement IC 3 IC 1 IC 2 ~7 mm ~5 mm Integrated high-q inductor, antenna design Move on-chip inductor from expensive Si to MC to reduce the cost.

2 Challenges for HD Fan-Out Electrical Design mm 7 mm 6 mm SI/PI with multilayer RDL on FO-WLP Signal path from chip to RDL to microbump/bga ball I/R drop analysis for Power Delivery Network Solution: Perform accurate ADS simulation, calibrate vs. Measurement IC 3 IC 1 IC 2 ~7 mm ~5 mm Integrated high-q inductor, antenna design Move on-chip inductor from expensive Si to MC to reduce the cost. Solution: Design Inductors, and provide accurate Si-verified models for Mobile applications. Parasitic, RLC, extraction for Fine pitch RDL PDK for HD FO-WLP Accurate RLC models for fine pitch RDL Solution: Design Technology characterization vehicle. Develop PDK mm Package Size vs. Application Smart Phone: 15 mm x 15 mm Tablet: 20 mm x 20 mm Routability of Bump/Pads to Package I/O Reduce # of RDL layers to reduce the cost. Optimize pitch, size and spacing of Interconnect. Solution: Develop EDA methodology with IME Fan- Out PDK P2

3 ~15 mm Applications: Phone vs. Tablet Test Vehicle 1 Test Vehicle 2 IC 3` IC 1 IC 2 ~7 mm ~5 mm IC 1 ~8 mm IC 2 ~6 mm ~15 mm Key Features # ICs Bump/Pad Count Package Size(mm*mm) Pitch (mm) ~20 mm Package Thickness (mm) Package I/O count TV 1 (application: Smart phone) 2 IC 1: Baseband processor with ~2500 pad, IC 2: RFA/PMIC with ~500 pad ~15* mm ball pitch ~0.45 ~ 1000 TV 2 (application: Tablet) 3 IC 1: AP with~4000 pad, IC 2:baseband chip with~1000 pad, IC 3: RFA/PMIC with ~500 pad ~20* mm ball pitch ~0.45 ~ 2000 P3

Electrical Test Vehicle SI/PI for Fine Pitch RDL Cu T=3 µm Polymer T=3 µm L=5 µm S=5 µm G

Dielectric Interconnect Thickness L/S R C RC Delay Cu-RDL (10mm) 3 µm 5 µm/5 µm 1.

68 fs/mm Simulation Measurement Challenges: Characterization and Design of low loss wide

RC characterization for interconnect, bumps (R and C) vs. Pitch, Cu-thickness, Layout 2.

4 Electrical Test Vehicle SI/PI for Fine Pitch RDL Cu T=3 µm Polymer T=3 µm L=5 µm S=5 µm G S G G Grounded Co-planar Waveguide Characterization of RDL Interconnects using Polymer Dielectric Interconnect Thickness L/S R C RC Delay Cu-RDL (10mm) 3 µm 5 µm/5 µm 1.12 Ω/mm ff/mm fs/mm Simulation Measurement Challenges: Characterization and Design of low loss wide bandwidth interconnects. Solution: 1. RC characterization for interconnect, bumps (R and C) vs. Pitch, Cu-thickness, Layout 2. Transmission line S parameter characterization (measurement and fullwave simulation) 3. ADS Channel Simulation Eye Diagram and comparison to Measurements on Vehicle 4. ADS Transient Simulation IR drop evaluation for PDN P4

5 Parasitic, RLC, extraction for Fine pitch RDL High Freq Measurements: C-V measurements RF Measurements Network Analyzer Meander Forks: M1-M3, RDL resistance and interline capacitance characterization Stacked Metals: RDL Line Capacitance Resistance Measurements: Four point Kelvin Structure Transmission Line Charaterization M1-M2; M2-M3 Daisy chains RDL chains for Resistance, Defectivity Scope of Work: Design and Characterization of comprehensive test structure suite for technology assessment, electrical modeling, PDK P5

Routability Analysis and EDA Flow with PDK HD Fan-Out PDK - Design Rules, DRC Deck -

X-Size Y: package Y-Size P w : Wiring Pitch Application, Design Inputs (IC size, I/O#)

6 Routability Analysis and EDA Flow with PDK HD Fan-Out PDK - Design Rules, DRC Deck - LVS, Parasitic Extraction - Cadence/Synopsys EDA Flow Total Available Routing Length.# RoutingLay ers. X. Y P w : Congestion Factor (empirical based on design, Line/Space, Via) X: package X-Size Y: package Y-Size P w : Wiring Pitch Application, Design Inputs (IC size, I/O#) Perform Initial Wiring Density Analysis, Stack estimate: Calculate Worst-case Delay/Maximum Operating Frequency. SI/PI Physical Implementation on EDA Platform HD-FanOut Analysis shows 4 µm RDL pitch allows adequate margin for routability for both TV-1, TV-2 Challenge: Verification on EDA flow for adequate electrical performance (SI/PI)

Q11 Integrated high-q inductor, antenna design L11 ANSOFT ANSOFT Integrated inductor on MC MC Si die # Turns=4 L = 2.59 nh @ 2.5 GHz Q = 14.31 @ 2.5 GHz Q max = 18.4, SRF = 17 GHz 20.00 17.50 15.

7 Q11 Integrated high-q inductor, antenna design L11 ANSOFT ANSOFT Integrated inductor on MC MC Si die # Turns=4 L = GHz Q = 2.5 GHz Q max = 18.4, SRF = 17 GHz m2 m1 XY Plot 2 Name X Y m m D80S13W Freq [GHz] 5.00 Inductor Q Factor Curve Info Q11 Setup1 : Sw eep $adj='0mm' $L='0mm' $w ='0.04mm' dia_via='10um' m1 m Freq [GHz] Inductor design on MC Structure Number of turns Trace width Trace spacing Coil area Challenge: Design and characterization of integrated high-q inductors on MC, and exploration of other IPDs on MC (e.g. antenna, filter) XY Plot 1 Name X Y m m Curve Info D80S13W11 L11 Setup1 : Sweep $adj='0mm' $L='0mm' $w='0.04mm' dia_via='10um' Inductance (nh) Q optimization P7

Silicon Interposers enable high performance capacitors

Silicon Interposers enable high performance capacitors Interposers between ICs and package substrates that contain thin film capacitors have been used previously in order to improve circuit performance. However, with the interconnect inductance due to wire