Substrates Lost in Translation

Transcription

1 2004 IEEE PRESENTATION Components, Packaging & Manufacturing Technology (CPMT) Society, Santa Clara Valley Chapter Substrates Lost in Translation R. Huemoeller Vice President, Substrate Technology March 17, 2004 Enabling a Microelectronic World As higher-function, higher-dissipation, and mixed-mode ICs reach the marketplace, The mix of packaging methods to accommodate these new devices reflects the complexity of their needs.

2 Substrates as Chip Translators A World in Transition Today s Packaging Migration Substrate Design Rule Evolution Substrates in Transition Substrates Lost in Translation A World in Transition Once upon a time, life was simple...

3 Changing Environment But technology refuses to stand still... A refrigerator with a detachable Web-ready HomePAD tablet computer built into its door. Samsung Electronics Communication has Transitioned from Wire-line...

4 ... to Wireless And from Voice Stream...

5 ... to Data Stream IC Packaging The Same Was True Once upon a time... packages were simple

6 Changing Package Environment Now they are incredibly sophisticated The New Paradigm... Technology Transitions - changing the way ICs are integrated at the system level

7 Example of Technology Transition System-in-Package MicroLeadFrame Camera Modules Stacked Die Chip scale BGA TouchChip Courtesy of STMicroelectronics MEMS Impact of Technology Transition IC packaging challenges are increasing Wafer size is growing Chip feature size shrinking Fab cost per chip shrinking Chip complexity increasing

8 Today s Packaging Migration 30% unit growth! Hot Packages

9 PBGA Substrate & Packaging Trends General Has NOT Kept up with Silicon Fab technology Results Longer wires = Thicker Au wire required to span = Higher Cost Added layers and laser vias required to route complex designs Lack of line/space progression in this space Substrate Technology Electrical management is minimal : very little impedance control Layer Count: 2 up to 6 Line and Space: 75 migrating to 50 um Bond Finger Pitch:175 migrating to 115 um Plating Technology: Elytic is std, but use of FBG, Etchback & Bussless (elytic) Package Trends Thermally Enhanced PBGA Bridging the price/performance gap between CD and std. PBGA C.D. Substrate & Packaging Trends General Slow Down in TELCO Market has caused Market to Shrink 70% 2004 is Predicted to be the First Year for Growth since 2000 Large Range of CD BGAs Ball count: 300 to over 1000 Body Size: 31 to 50mm Substrate Technology 1 to 10 Metal Layers, 1 to 3 bonding tiers eptfe, Polyimide, and BT dielectric Thermal & electrcal management is critical Up to 40W in some cases : avg 15W Packaging Trends Large price gap between PBGA & CD BGA Many new TELCO chips going into F/C packages Proven W/B substrates up to 12 Gb/s

10 Tape CSP Substrate & Packaging Trends General Shrinking Packaged Tape Supply Base High Density tape substrate packages converting to laminate Lower costs and addition of ground planes makes this attractive Two metal tape packages still price prohibitive Substrate Technology Remaining Supply Base = 5 SST, LGM, H.Cable, Compass & Toppan All others withdrawn from high density tape packaging However, many new players to Camera Flex Packaging Trends Camera Module thriving in tape substrate platforms Low density, uncomplicated Fits different supply stream than high density packages Parlex, Interflex, MekTec, Mflex Rigid CSP Substrate & Packaging Trends General Density, Density, Density Massive growth in hand-held market Substrate Technology Via Density : 400k + vias / sq. meter Pattern Density : 50um L/S common Surface Finish Selective OSP finish of choice Packaging Trends Stacked Die Packages Getting Thinner 4 Layer Ultra Thin CSP = 220 um +/ _ 30um Packages Getter Smaller / Denser 0.5mm & 0.4mm ball pitch Transition to FC to reduce inductance of wires Concerns with Impedance for MCM

11 SiP Substrate & Packaging Trends General RF Modules generally do not require advanced design rules Higher levels of integration will drive adoption of more 4 layer stack-ups for RF Modules Transition from custom core materials to standard materials Substrate Technology 65um line/space, 250 um drilled vias, >0.2 mm core, etc. Exotic materials used when embedding transmission line structures in the laminate Selective Ni/Au plating for improved reliability Double image processing Packaging Trends MCM SiP Embedded BALUNs & Filters Flip-Chip SiP Si/SiGe FC : Sn/Pb Eutectic GaAs FC : Copper Pillar FC Substrate & Packaging Trends General Material cost is 60-80% of flip chip cost Substrate Technology Most advanced set of materials & design rules used Material cost will determine future of flip chip Addition of layers driving functionality but also driving cost Four clear segments of substrate technology today Packaging Trends Broken into cost segments and sophistication HDI I = (1-n-1) : 100um Line Pitch HDI II = (1-n-1), (2-n-2) : 80um Line Pitch HDI III = (3-n-3), (4-n-4) : 40um Line Pitch HDI IV = (Core-less) : 30um Line Pitch = Mixed Costs = Cont. Margin : Volume = High Cost : but dropping = Highest Cost

12 Flip Chip Substrate Options HDI I (1-N-1) Virtually all structures use glass reinforced structures with lased vias Very little heat dissipation concerns HDI II (2-2-2) Two Methods - Reinforced Glass on core or ABF on Core Heat management necessary for processors HDI III (3-N-3 + & 5/7 Lyr eptfe) Two Methods ABF on Core or eptfe Buildup All packages require heat management Flip Chip Substrate Options Supply Base & Technology Flip Chip Tier IV = Core-less Structures Filled via structures Drop down connections no stagger

13 Substrate Material Transitions Embedded Components Embedded Resistors Very costly and too large for packages Good for Motherboards, not practical for substrates Embedded Capacitors Two Choices : Thick film or Thin film Barriers to Technology Emergence: Design Tools Needed Testing known good passives Cost : need 6-8 components/ sq.cm to be competitive Embedded Planar Structures Inductors, Baluns and Filters Designed into substrate Substrate Design Rule Evolution

14 Substrate Design Rules Wirebond Substrates Bond Finger Pitch Bond Finger Width Bond Finger Space Pattern Width / Space -R -T / / / / / / / / 15 Laser Via / Pad Size / / / / 125 Mech Via / Pad Size / / / / 200 Cu Foil / Plating 10 7 / 10 5 / 10 3 / 10 3 / 5 Substrate Design Rules Flip Chip Substrates The Break-down Core Design Rules Min Core Thick - Desired Core Material Type Laser Min Via Pad Size Laser Min Via Size Mech Min Via Pad Size Mech Min Via Size Min Line Width / Space Via Fill Material (mm) Glass Reinforced BT HS, E679F(G) / / /30 BT/PHP BT/PHP BT/PHP Film Based BT, E679F(G), R5715S (L) /50 40/40 30/30 PHP900 DC5-4, IR6, THP1000 DX1 eptfe Cu Cu Cu 200 clearance Etched Core Clearances N/A PTFE B.U. Design Rules Min Dielectric Thickness Min Via Drill / Pad Size Min Line Width / Space Max B.U. Layers Min Trace Plating Thickness Min Via Plating Thickness Bump Pad Size / Pitch S/M Type and Thickness S/M Min Registration Toler /220 80/150 60/100 35/35 30/30 25/ / / /200 AUS 303/703, BGX700 20µ /100 50/90 50/80 25/25 20/20 15/ / / /150 BGX5E, AUS703, SR7000/7200G 15µ /110 50/90 35/90 25/25 25/25 20/20 4 per side LPI/PTFE Glass Film eptfe

15 Substrate Supplier Trends Flip Chip Substrates Core Transitions Historically : 800 µm core PTH pitch & 100 µm line and space Today, density of chip is forcing migration Thinner cores 0.8mm to 0.4mm Multilayer cores More signals through the core Substrates in Transition

16 Substrate Innovation Stagnating Why are Suppliers not Investing?? Prices Will Not Drop Below This Pt Total Cost To Manufacture PBGA 4L PBGA 2L 4 Lyr & 1-N-1 SiP Rigid CSP 1-N-1 PBGA Tape CSP FC 3 + -N-3+ FC 1-N-1 FC 2-N-2 Margin Operation Break Even New Solution Required BGA Board Manufacturing Trends Exited HDI Mother Board PBGA PBGA CSP SBGA CSP PBGA Adv-PB, SiP Adv-C CSP PBGA, FC Adv-PB, SiP Adv-C CSP, WL PBGA, FC Adv-PB, SiP Adv-C KCC Hadco SMST Merix CCI ACL Astron Advanced Motherboard DDE PBGA KCC Eastern WUS DTI Advanced BGA Boardtek Compeq Interposer BGA LG Unicap JCI, SSE PPT CCI Kinsus IBI, KCC LG NanYa, IBI, SGTi NanYa, LG, UMTC SSE UMTC SGTi ST JCI, IBI SSE UMTC Kinsus,Kyo NanYa IBM, KYO IBI Who Next? DTI Need Investment Opportunity Std Drill 225k Vias Std Image 75um L/S Std Cu Pattern Plate Adv Drill k Vias Adv Cu Pattern Plate Adv Image 45um L/S SOA Drill 400k+ B-Vias SOA Image 20um L/S Via Fill Pattern Plate SOA = State of Art

17 BGA Board Manufacturing Trends Std Cost Adv Cost $200 Sq. M $250 Sq. M $400 Sq. M Motherboard Needed Growth PBGA Advanced BGA CSP, FC, SiP Lasers Steppers Glass AW Low Cost Laminate ENIG Select OSP Bussless Std Drill Adv Drill Std Std 225k Drill Std Plate Std 400k Image Plate Vias Vias Std Image > 65um Adv Image < 50um Adv Plate Shut Substrates Lost in Translation

18 Translating Die Complexity Substrate vs. Interposer Substrates are Slipping Further Behind Foundry Technology 130 & 90-nm processes are maturing, but still have challenges: Copper Metalization Low-K Dielectric Mixed Signal Integration - SoC I.C s need a translator to the motherboard Interposer has moved directly into critical path of wafer fabrication roadmap Wafer Level Interposers Using thin film techniques for interstitial via connection to die (RDL) Not a substrate. merger of die & package technologies Interposer manufactured at back-end or front-end Wafer Level Interposers Wafer level CSP Technology where most or all of the process steps are carried out at the wafer level (RDL) Method of choice to translate from die to motherboard for true CSP Why? Able to redistribute with 15um lines/spaces Doing it better, cheaper with new solutions Only real potential 0.3mm solution known However, WLP today is most appropriate for low pin-count, small chips

19 Translating Die Complexity Substrate vs. Interposer Interposer Negates Need for Substrate ISP s (Integrated Service Providers) Filling space once owned by substrate fabricators and assemblers Translating the Die The Substrate Gap RDL & Bump technologies have won the 1st round However, limited to fan-in approaches only I/O And, limited in routing complexity > 100 I/O, much more costly, compliant bump approaches required

20 Translating the Die An Opportunity? Yes!! The Industry Needs a New Solution The Ideal Scenario. simplification of the process!! Extreme miniaturization Lower manufacturing costs Better reliability Better performance Translating the Die Ultimate Interposers 250um 250um 250um 250um 25um L/S B.U. Best in Class Substrates Today 100um 18um L/S Adv.Tape 30um 10um L/S Ultimate Interposer 10 Channels of Routing in Reinforced All Vias are Pad-less

21 Translating the Die Re-Designed into Took 37.5mm 1156 I/O All Routing on Single Plane Translating the Die Ultimate Interposers 10 µm lines 10 µm spaces Aramid 10 µm lines 10 µm spaces eptfe Multiple Dielectrics Possible

22 Translating the Die The Ultimate Interposer A Giant Step Forward 1. Recessed features prevent migration and shorting 2. Reduction in number of steps to manufacture a substrate 3. Potential elimination of Ni, Au interconnects Cu only interconnects possible 4. Dielectrics can be tailored to electrical needs 5. Choice of buildup on wafer 6. Very high yielding process 7. Reduced die size and die pad / pitch as a result 8. Better thermal performance 9. Extremely dense due to miniaturization 10. Lower Cost ~ Industry Changing Technology ~