Organic Packaging Substrate Workshop Overview

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1 Organic Packaging Substrate Workshop Overview Organized by: International Electronics Manufacturing Initiative (inemi) Mario A. Bolanos November 17-18,

2 Organic Packaging Substrate Workshop Work Shop Coordination Team Jie Xue Cisco John Savic Cisco Hamid Azimi Intel Charan Gurumurthy Intel Kazuko Inaba Intel Mario Bolanos TI Luis Rivera TI Bob Pfahl inemi Haley Fu inemi 2

3 Organic Packaging Substrate Workshop Speakers and Companies Jie Xue Hamid Azimi Hirofumi Nakajima Luis Rivera Bernd Appelt JaeYoon Kim Kenny Lee Masaru Takada Koichi Nonomura Kozo Yamasaki Steve Yang Richard Sheridan Cisco Intel NEC TI ASE Amkor STATS ChipPAC Ibiden Kyocera NTK NanYa UMTC 3

4 A CASE FOR ACTION 4

5 Organic Substrate Potential show stopper? ITRS Assembly and Packaging Difficult Challenges (>32nm) Near Term Close Gap between Chip and Substrate Improved Organic Substrate (increased wire ability at low cost; increased via density in substrate core.) ITRS Assembly and Packaging Difficult Challenges (<32nm) Long Term Package Cost Does not follow the Die Cost Reduction Curve (increased device complexity requires higher cost packaging solutions) Substrate cost is >> 50% of total package cost inemi 2007 Roadmap Organic Substrate Research Needs High performance laminates that are competitively priced: low dielectric constant; low loss inemi 2007 Roadmap Identified Gaps and Showstoppers The major showstopper affecting the interconnect industry is the precipitous decline in substrate R&D investment Source: Mario A. Bolanos, Packaging Technology Challenges for Future CMOS Cu Ultra Low K Devices, IMEC October

6 Anantha Chandrakasan 6

7 Work Shop Objectives Main Objectives: Identify gaps in organic substrate technology that need to be addressed to facilitate the continued advancement of electronics packaging. Identify issues and needs that are potentially best solved by consortium activities. Set the priorities and direction for future collaborative efforts on organic packaging substrates. Form action groups to execute the required industrial collaborative programs. 7

8 R&D Pre-Competitive Collaboration Model Collaboration OEMs and IC Companies Organic Substrate Technology Gaps and Roadmap Packaging Assembly Companies Substrate Providers inemi Provides the Opportunity for International Consortia Collaboration 8

9 R&D Pre-Competitive Collaboration Model NEC CISCO TEXAS INSTRUMENTS INTEL OEM s and IC Companies Product Focus Future Products and Packaging Technology Roadmap Requirements Microprocessor - FCBGA Portable Handset FCCSP and POP Networking Products Minimize High Temp. Package Warpage STATSChipPAC AMKOR ASE Packaging Assembly Houses Packaging Focus Required Organic Substrate and Packaging Technology Needs to Support New Products Assembly Challenges using Organic Substrate Technology Advanced Package Solutions for Graphics and Chipset Mobile platform packaging challenges Substrate Suppliers OEM s and IC Companies Packaging Houses NTK UMTC NANYA KYOCERA IBIDEN Organic Substrate Suppliers Substrate Focus Organic Substrate Technology Roadmap to Support Future Packaging Technology Strip format CSP/POP applications Large body organic FCBGA PBGAs and strip format CSPs Small/mid body size FCBGA organic, CSP/POP Low inductance embedded capacitance Technology 9

10 Key Themes and Focus Three key themes were identified as a means to guide speakers in preparing their presentations. Aligning Substrate Roadmaps and Bridging Gaps Standardized Evaluation of Key Substrate Performance Outputs and Reliability Priorities for Consortia Activities 10

11 Key Themes and Focus Aligning Substrate Technology Roadmaps General needs: Finer lines and spaces, PTH/via pitch, meet inemi roadmap Cost parity and/or immediate cost effectiveness for new technology FC-CSP/POP: Warpage on POP applications - understanding interactions with assembly processes and mold materials Standardization of pad surface finish Speed of time to entitlement of yield and cost with advanced design rules (<20/20 um) Roadmap and implementation plan for 15/15um line/spaces Inspection (AVI) and Test 11

12 Key Themes and Focus Aligning Substrate Technology Roadmaps FCBGA: Minimizing package inductance: enabling reliable thin substrate technology and fully stacked micro-via interconnects for large package size applications. Manufacturing strategy for thin core and core-less. Advanced materials/processes: Lower loss, improved impedance control, lower CTE mismatch, and improved reliability. Warpage minimization with thin core and large body size packages. Embedded actives/passives: Current capability for core power decoupling, test challenges. With the emergence of 3D TSV stacking products, what is the organic substrate roadmap to accommodate TSV stacked modules and potential new key challenges (e.g. power dissipation). Larger package size roadmap for CMOS 28nm nodes and beyond. What are the realistic limits from manufacturability, warpage, etc. of package body sizes larger than 55mm organic?. Package level EMI shielding. 12

13 Key Themes and Focus Standardized Evaluation of Key Substrate Performance Outputs and Reliability: Convergence of materials and processes. Measurement and reporting of key substrate electrical. Performance attributes. Reliability testing and process characterization. Balancing convergence strategies for high volume with adaptability for low volume. Speed of process yield entitlement. Consortia Activities: Areas of engagement and collaboration. 13

14 Organic Substrate Technology R&D Needs Research Needs High performance laminates, with low dielectric constant, low loss that are competitively priced. Integral materials for resistors, capacitors, inductors. Self reinforced materials. Liquid crystal polymer compatible with current PCB manufacturing. New non-contact testing techniques. Boards without surface finishes. Improved dimensional stability materials Waveguide materials and manufacturing techniques. Alternate patterning processes (imprinting, inkjet printing, mask less patterning). Non solder based interconnects. Novel lower cost materials and high output, high yield processes Development Needs Microvia technology improvement. Microvia metallization. Continuous cycle time reduction for quick turn substrates. Flexible circuit quick turn facilities. Improved design tools for emerging technologies like embedded passives and optoelectronics PCB s. Layer alignment accuracy. Finer line and space development. Improved drilling for less roughness and less run out. Pad surface finish alternatives Flip Chip pad design for non solder bump interconnect. Silicon carriers development. Fast time to yield entitlement with new advanced design rules. Source: inemi Roadmap 14

15 Major Opportunity for Improvement NOW! Faster time to process yield entitlement when new substrate technology and design rules are implemented Speed of yield entitlement and sustaining high yields over time is a major concern. It affects substrate cost, capacity, cycle time and time to market. To be cost competitive, substrate process yields at high volume need to be in the 90 s Time to yield entitlement from prototypes to high volume needs to improve to only a few months vs. several quarters. This issue if not addressed will continue to get worst as we continue to stretch current technology to its limits Product development methodology, process, material and production equipment selection need to include high process yield requirement As new substrate technologies and design rules are implemented, in addition to process and manufacturing improvements there is a need to develop better final substrate inspection and testing capabilities. Automatic Visual Inspection (AVI) and Open and Short (O/S) Test capabilities need to be developed 15

16 Organic Substrate Technology Gaps and Roadmap Requirements Higher Levels of Integration Higher wiring density High freq,/performance Cost Competitive $$$ More Miniaturization Thinner and smaller packages Higher thermal dissipation New Materials Thermo Mechanical Properties Electrical Properties What are the limits of current technology? Optimization Chemical Properties High Yields and Manufacturability Where can current technology stretch to? New Processes Innovations Breakthroughs Cost Competitive Future Substrate Technology 16

17 I applaud all companies that are here today for supporting this initiative to work together to address an industry level priority in a cooperative precompetitive R&D model. This is a new model and potentially the beginning of a new era in our industry. Thank You 17

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