Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller

Transcription

1 Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller Corporate Vice President, WW RnD & Technology Strategy 1

2 In the Beginning ewlb 2

3 Fan Out Packaging Emerges Introduction of Fan Out (ewlb) Marketed as package replacement for fccsp Limited in application and use at initial stages 54M units shipped in M units shipped in 2015 far short of earlier predictions at that time Fan Out market struggled 3

4 Today (2016) 4

5 2016 Has Become the Year of Fan Out Expected ~ 2 billion packages to ship this year So what changed? 5

6 Mobile Market: Space & Performance The need for more space and performance are key triggers Traditional Fan Out More space for larger battery Thinner and smaller than fccsp Convergence of WLCSP to Fan Out Same BGA pin out on advanced nodes to address die shrink Advanced Fan Out InFO Performance! Electrical, power, thermal 6

7 WLFO Traditional Applications and Drivers Main applications Mobility CODEC RF Switch/Transceiver PMIC Automotive RF radar Connectivity Primary drivers Form factor reduction Fine feature size (advanced photo lithography) Multi-die and 3D capability Strong electrical performance (mmw capable) CODEC RF Transceiver MCU PMIC NFC 7

8 Advanced Fan Out Value Proposition Reduced Z-height & form factor Enhanced signal integrity Superior impedance matching Optimized power distribution Improved thermal performance/junction temperature Ability to address multi-die heterogeneous integration (SiP) 8

9 Simplified Wafer Level Process Flow Advanced Fan Out Chips Last/RDL First POP Pillars 200 µm Pitch RDL for Memory Interface SWIFT 40 µm Pitch < 0.30 mm Total Height Carrier Remove Top Side Routing For Memory Interface Carrier Carrier RDL & Copper Pillar Bump (3D Only) Chip Attach & UF Wafer Mold 9

10 Tomorrow 10

11 Millions of Packages Fan-Out WLP Market Projections 7,000 6,240 5,831 6,000 5,113 5,000 4,000 3,481 3,000 2,001 2,000 1, TechSearch International, Inc. Device types driving HVM include RF transceiver and switch, PMIC, CODEC, automotive radar, connectivity (IoT) modules, Apple's application processors made by TSMC and application processors from other companies in future Future memory for top PoP Many multi-die products in future 11

12 Fan Out Market 2017 Traditional Fan Out gaining momentum Large activity in mobile market RFIC, PMIC, CODEC Product Body Size Total Units (M) RFIC CODEC PMIC Other 3 mm 4 mm 6 mm mixed Totals. See TechSearch Courtesy of TechSearch International, Inc. 12

13 Thousands of 300mm-Equivalent Reconstituted Wafers Projected Wafer Demand for FO-WLP (300mm equivalents) 10,000 9,000 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,345 2,929 6,261 8,669 9,292 Device types driving HVM include RF transceiver and switch, PMIC, CODEC, automotive radar, connectivity (IoT) modules, application processors Assumes 80 µm die street 1, TechSearch International, Inc. Assumes high-yield process of 99% 13

14 Emergence of Advanced Fan Out SWIFT TM Process RDL first Chip attach last Cycle time & yield Flexibility & scalability Performance Shorter cycle time RDL wafer pre-build Known good RDL wafer Package variants 3D, SiP etc. Multi-die, passives Flexible thickness Thermal Electrical Reliable 14

15 Advanced Fan Out Comparison Key Attributes Fan Out SWIFT fccsp Exp Die PoP fccsp Fan-in PoP SWIFT Benefits Package Thickness mm 0.47 mm mm 4% reduction 31% reduction Layer Count 3 or Construction Electrical Interposer Interconnect to Package Edge 3 layers on bottom + 1 layer on top (if fan in) Reduced signal width allows flexibility in routing/impedance control 3 layer substrate on bottom Predetermined location at edge of package 3 layer substrate on bottom + 2 layer substrate on top Fixed signal widths and difficulty in impedance control Same as exposed die Fewer layers Flexibility, reduced trace length, reduced DC resistance & AC loss 50 µm 200 µm 200 µm 75% Reduction 15

16 DDR4: Signal Integrity Comparison Key Attributes Fan Out SWIFT fccsp Exp Die PoP SWIFT Benefits Eye Diagram 6 Gbps Eye Amplitude 548 mv 451 mv 3.0x Improvement Eye Height 481 mv 339 mv 1.4x Improvement Eye Width 164 ps 158 ps 4.0x Improvement Pk-Pk Jitter 3.7 ps 9.8 ps 2.2x Improvement Rise/Fall Time 64 ps 75 ps 1.2x Improvement 16

17 DDR4: Signal Integrity Comparison Key Attributes Fan Out SWIFT fccsp Fan-In PoP SWIFT Benefits Eye Diagram 6 Gbps Eye Amplitude 638 mv 444 mv 5.0x Improvement Eye Height 551 mv 318 mv 5.0x Improvement Eye Width 159 ps 145 ps 3.0x Improvement Pk-Pk Jitter 7.9 ps 14.1 ps 1.8x Improvement Rise/Fall Time 63 ps 75 ps 1.2x Improvement 17

18 SerDes: Signal Integrity Comparison Key Attributes SWIFT fccsp Exposed Die PoP SWIFT Benefits Eye Diagram 8 Gbps Eye Amplitude 998 mv 995 mv 4.0x Improvement Eye Height 954 mv 882 mv 3.0x Improvement Eye Width 125 ps ps 0.5x Improvement Pk-Pk Jitter.01 ps.07 ps 6.0x Improvement Rise/Fall Time 29 ps 32 ps 1.4x Improvement 18

19 SerDes: Signal Integrity Comparison Key Attributes SWIFT fccsp Exposed Die PoP SWIFT Benefits Eye Diagram 16 Gbps Eye Amplitude 995mV 993 mv 2.0x Improvement Eye Height 826 mv 604 mv 2.3x Improvement Eye Width 55 ps 50 ps 5.0x Improvement Pk-Pk Jitter 2.9 ps 4.8 ps 1.8x Improvement Rise/Fall Time 19 ps 31 ps 1.5x Improvement 19

20 SerDes: Signal Integrity Comparison Key Attributes SWIFT fccsp Fan-In PoP (MEP) SWIFT Benefits Eye Diagram 8 Gbps Eye Amplitude 1098 mv 1001 mv 5.0x Improvement Eye Height 934 mv 906 mv 3.3x Improvement Eye Width 122 ps 118 ps 4.0x Improvement Pk-Pk Jitter 2.5 ps 6.25 ps 2.5x Improvement Rise/Fall Time 36 ps 42 ps 1.4x Improvement 20

21 SerDes: Signal Integrity Comparison Key Attributes SWIFT fccsp Fan-In PoP (MEP) SWIFT Benefits Eye Diagram 16 Gbps Eye Amplitude 1009 mv 1007 mv 0.1x Improvement Eye Height 799 mv 361 mv 9.0x Improvement Eye Width 55 ps 53.9 ps 1.0x Improvement Pk-Pk Jitter 7.8 ps 7.8 ps equivalent Rise/Fall Time 26 ps 41 ps 1.4x Improvement 21

22 Power Integrity: Lower PDN Impedance FC PoP FC PoP 89% Impedance Reduction SWIFT SWIFT PCB PCB MHz PDN Impedance: Improved by 11% vs FC PoP (at 250 MHz) SWIFT : Substrate eliminated resulting in reduced pad-bga wiring length Low PDN Impedance High power integrity 22

23 Noise: Signal Integrity Comparison Insertion Loss SWIFT s controlled impedance has a wideband low pass filter effect essential for PCIe and Ethernet applications Return Loss Improved by 6 2 GHz Cross-talk Improved by 6 2 GHz 23

24 /W SWIFT vs FC PoP Thermal Simulation Steady State Analysis Max die temperature (3W dissipation) Theta JA FI-PoP SWIFT FI-PoP SWIFT JEDEC Mobile phone 10 JEDEC Mobile phone Max Temp C (3W) FC PoP SWIFT Delta Delta % Theta JA C/W FC PoP SWIFT Delta Delta % JEDEC % Mobile Phone % JEDEC % Mobile Phone % 24

25 Temperature, Temperature, SWIFT vs FC PoP Thermal Simulation Transient Analysis JEDEC FI-PoP SWIFT Mobile Phone FI-PoP SWIFT Time for die temp to reach 105 C (9W power dissipation) JEDEC Mobile Phone fcpop 19.5 sec 20.5 sec seconds seconds Time, sec Time, sec SWIFT 28.2 sec 36.8 sec 8.7 sec 16.3 sec Gain 45% 80% Time to reach the allowable max die temperature when a 9 watt duty cycle is applied The assumed allowable max die temperature is 105 C SWIFT extends the time to reach 105 C by approximately 9 and 16 seconds as compared to conventional substrate FC PoP 25

26 Advanced Fan Out SWIFT TM and InFO Mobility Apps-Processor Baseband (Logic + Memory) Power Management Display Driver (SiP) Drives Performance Reduced form factor Enhanced signal integrity Superior impedance matching Optimized power distribution Improved thermal performance 26

27 The Future 27

28 Future: Traditional Fan Out which direction? Relative Cost Comparison Higher $ As package to die ratio increases, there is more disparity between Fan Out and low cost fccsp Fan Out [1ML] fccsp fccsp Approximate price parity Lower $ WLCSP Fan Out [1ML] Die Size mm (WLCSP) Die Size mm Die Size mm Die Size mm Die Size mm Die Size mm Die Size mm Die Size mm 28

29 Future: Advanced Fan Out Package Roadmap All About Performance Available Single Die PoP 3D tall Cu interconnect Land side cap Wafer Level SiP Active and passive components Sputtered EMI shield SWIFT on Substrate Split logic 3D Interconnect Land-side cap Multi-Die PoP 3D tall Cu interconnect Land side cap Fan-in RDL 29

30 Summary Fan out packaging addresses needs from very small, low I/O devices all the way up to large die, high end processors Fan out enables the most complex SiP solutions, such as mobile RF front-end or MEMS technologies, with package form factor reduction Traditional fan-out will continue to be pressured by lower cost substrate technologies Advanced fan out is uniquely suited: to improve product performance to handle multiple die from different functional blocks (analog, mixed-signal, digital) to enable very small form factors 30

31 Thank You 31