The Future of Packaging ~ Advanced System Integration

Transcription

1 The Future of Packaging ~ Advanced System Integration Enabling a Microelectronic World R. Huemoeller SVP, Adv. Product / Platform Develop June 2013

2 Product Segments End Market % Share Summary 2

3 New Product Technology Focus 3

4 Market Direction & Drivers 4

5 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 5

6 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 6

7 Interconnection : Fine Pitch Cu Pillar Driven by Demand for Handheld, High Performance, Low Power Devices Provides Significant Improvement Over Solder Bump Launched in 2010, ~ 200 Million Units Sold WW Industry-Leading Platform Being Adopted by Most Customers Enabling Technology for 2.5D and 3D Packaging with Through Silicon Vias 7

8 Why the Need for Cu Pillar? Technology Trends Devices Function Integration in All Three Dimensions Silicon Node Shrinks But Die Size Remains Unchanged Increased I/O Density Finer BGA Pitch More Demanding Warpage and Coplanarity Criteria Digital Baseband Applications Processor Networking ASICs Digital TV ASICs Power Management Embedded Processing DSP, MCU, Digital Media 8

9 Fine Amkor Pitch FPFC Cu Pillar Technology Formats From Standard CSP Package Structure To Broad Package Application PSfcCSP fccsp TMV PoP FCBGA 9

10 Foundational Blocks for Advanced Integration Cu Pillar TSV Thermal & Adv. Materials High-End FC WLFO 10

11 Integration : Through Silicon Via (TSV) Current Status World s first production fully integrated TSV package platform completed Logic dies on Si interposer product is being produced Large number of customers engaged in active TSV development Future Target devices Logics on Si interposer Logics + memories on Si interposer Memory / Memory stack Memory / Logic combination 11

12 2.5D Multi-Chip Interposer Breakdown High End Products : Networking, Servers Silicon interposers ; < 2um L/S, < 15nsec latency, > 25k µbumps per die Several foundries delivering silicon interposers today Others in consideration of adding capability to make use of unused assets Mid Range Products : Gaming, Graphics, HDTV, Adv. Tablets Silicon or Glass interposers ; < 3um L/S, < 25nsec latency, ~10k µbumps/die Glass may provide cost reduction path in future Glass interposers infrastructure still immature, but improving Low Cost Products : Lower End Tablets, Smart Phones Organic interposer?? ; < 8um L/S, low resistance, ~2k µbumps Must provide cost reduction path to enable this sector ; thick copper traces Possible elimination of laminate substrate, but organic interposer as substrate!! 12

13 Memory Sources End customer choosing memory supplier Memory supply chain is constrained today 2 different sources Elpida (Micron) & Hynix Logistics Plan is to receive memory as KGM on tape and reel End customer will manage logistics through consignment models Activity Multiple programs in progress with stacked memory in wide I/O format HBM or Wide-IO2 Shipping single die, 2 die stacks and 4 die stacks already Most development being completed with 4 die stacks now 13

14 Package Migration to TSV SiP-MCM Integration TSV Product Demand (300mm eq. wafers) Wafer Shipments (in 1000 s) D-ICs, old forecast 3D-ICs, new forecast TSV Interposers Courtesy of TechSearch International, Inc

15 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 15

16 Embedded Die : 3 Levels of Architecture Substrate Level Passive Components Active Die Wafer Level Die Single Die Multi-Die 3D Package Single Die Multi-Die 3D Pkg Passive integration Internal EMI shielding possibilities Multi-die capability more than one die may be embedded Two-sided construction top side components may be mounted 16

17 Embedded Die in Substrate Embedding Active Die : in small volume production today 5x3mm embedded die, 12mm body, 6Layer substrate, 536 Balls Passed package reliability : MRT L3 260C ; HAST 96hrs, TCB1000, HTS 1k-hrs PCB to Die:185 um Inner Die: 185 um PCB: 400 um Top Die Embedded Die 65 mm Laser Via 17

18 Embedded Die in Substrate (cont d). Embedding Passive Die : in high volume production today Passive Component (MLCC : 100nF, 1.0 x 0.5mm) fcpip, 1x1mm embedded IPD, 15BD, 4Layer, 603 Balls passed MRT L3 260 C ; HAST 96hrs, TCBx1000, HTS 1000hrs Passive Die (IPD : 100nF, 1.0 x 1.0mm) fcpip, 1x1mm embedded IPD, 15BD, 4Layer, 603 Balls passed MRT L2aa 260 C ; HAST 96hrs, TCBx1000, HTS 1000hrs 18

19 Advanced Platform : Wafer Based Fan Out Embedded die on Wafer Product capability up to 15x15mm, 0.4mm pitch, 1000 I/O+ 300mm formats Fully deployed for several years now 19

20 Advanced Platform : Wafer Based Fan Out (Cont d) Customer Interest Hybrid Packages, RF Connectivity, Audio modules & Sensor Applications No Wire or Substrate Die Shrink Continuing Entry Large I/O Count Without Die Increase niche Face to Face PoP/Sensor Application Expand 3D PKG Platform Creation growing Die Die Cost Reduce Core Technology Development Customer / Product Base Widens 20

21 Market Growth for Wafer Fan Out Packages Single die solutions remain niche to market ; primarily one customer driving use 21

22 Evolution of Wafer Based Fan Out Wafer Fan Out 3D Products Customer interest expanding to two sided structures Requiring more functionality Ultimate goal is multi chip in smallest form factor. H Thru Mold Via 3D-WLFO Benefits Die Die Die Die Die Die Die Die Die Die 3D-WLFO Benefits 22

23 Market Growth for Wafer Fan Out Packages Multi die solutions will drive future market ; triggers growth phase 23

24 Embedded in Panel : Future of Embedded Die 200mm Phase 1 300mm Phase 2 300mm 300mm 3D Phase 3 Panel 3D Development Well Underway Phase 4 24

25 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 25

26 Advanced Flip Chip Continuing to Drive Growth 26

27 High Performance Flip Chip Industry Direction Increasing body size (>55mm BD) Increasing die size (>26mm) 32/28nm in production with 20nm qualification in progress Cu Pillar to enable density / pitch below 150um bump pitch Coreless substrates in use for 32/28nm Multiple die per package. With die count continuing to increase 27

28 Advanced FC Packages : Chip on Chip Next Generation of FC CoC POSSUM MEMs, Automotive, Networking 28

29 Advanced FC Packages : Chip on Chip, cont Targeted production Networking Microcontroller Automotive Heat Spreader ASIC + FPGA LOGIC Substrate ASIC + Memory ASIC + Memory 200um bump pitch LOGIC (780um thickness) 40um bump pitch CoC Technology ASIC (60um thickness) Cu pillar with LF solder + microbump 29

30 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 30

31 Advanced Materials Enabling Package Integration Die Attach Substrate Underfill Material & Equipment Technology Enabling System Integration Thermal 31

32 Advanced Packaging & Technology Integration Copper µpillar Bumping Die Joining Adaptive Learning Required Silicon Interposer Substrate Underfill Thermal Sub-assembly & Package Warpage 32

33 Foundational Blocks for Advanced Integration Cu Pillar TSV Advanced Materials Advanced Flip Chip Embedded Die 33

34 Smaller Form Factor Larger Advanced Package Integration Becoming Clearer Board Level LOGIC CoC possum ASIC Wafer Level Die Die Level Interconnect Density & Functionality : Increasing 34

35 Package Migration to SiP - MCM Integration 35

36 Advanced Silicon Nodes Driving Higher Costs 36

37 SOC to 2.5D TSV MCM SiP Drivers Monolithic 22nm SOC Type 1 Logic 1 Logic 2 Logic SoC Logic 3 Logic 4 Logic 1 Logic 2 Logic 3 Logic 4 Multi-Die Interposer SiP Monolithic 22nm SOC Type 2 Logic 1 Cache Analog SoC Logic 2 Logic 1 Logic 2 Logic 1 Logic 1 Logic 2 Cache Analog Multi-Die Interposer SiP Focus Process Node Development on Specific Application Functionalities Reduces complexity and mask layer count of process node Improves wafer yield Reduces wafer start cost Improves performance, power, and area of each application 37

38 Industry Advanced Package Integration Roadmap Commissioned report September 2011 courtesy of Amkor Technology and Yole Développement 38

39 Smaller Form Factor Larger Amkor s View : Future of Advanced Package Production Transition Developing Si Photonics + TSV Die Die All About System Modularity & Integration Interconnect Density & Functionality : Increasing 39

40 Thank You! Enabling a Microelectronic World